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74AUP1G885 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G885 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 19 page 74AUP1G885_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 26 June 2009 3 of 19 NXP Semiconductors 74AUP1G885 Low-power dual function gate 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 2. Pin configuration SOT765-1 (VSSOP8) Fig 3. Pin configuration SOT833-1 (XSON8) 74AUP1G885 AVCC B1Y 2Y C GND n.c. 001aae354 1 2 3 4 6 5 8 7 74AUP1G885 C 1Y VCC n.c. 2Y B A GND 001aae355 36 27 18 45 Transparent top view Fig 4. Pin configuration SOT996-2 (XSON8U) Fig 5. Pin configuration SOT902-1 (XQFN8U) 001aaj897 74AUP1G885 Transparent top view 8 7 6 5 1 2 3 4 A B 2Y GND VCC 1Y C n.c. 001aaf630 B C A 2Y 1Y n.c. Transparent top view 3 6 1 5 7 2 terminal 1 index area 74AUP1G885 Table 3. Pin description Symbol Pin Description SOT765-1, SOT833-1 and SOT996-2 SOT902-1 A, B, C 1, 2, 6 7, 6, 2 data input GND 4 4 ground (0 V) n.c. 5 3 not connected 1Y, 2Y 7, 3 1, 5 data output VCC 8 8 supply voltage |
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