74AUP2G32GM datasheet(2/17 Pages) NXP

No. de pieza	74AUP2G32GM

Descripción Electrónicos	Low-power dual 2-input OR gate

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Fabricante Electrónico	NXP [NXP Semiconductors]

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2 / 17 page

74AUP2G32_3

Product data sheet

Rev. 03 — 8 January 2009

2 of 17

NXP Semiconductors

74AUP2G32

Low-power dual 2-input OR gate

3.

Ordering information

4.

Marking

5.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74AUP2G32DC

−40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74AUP2G32GT

−40 °C to +125 °C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1

× 1.95 × 0.5 mm

SOT833-1

74AUP2G32GD

−40 °C to +125 °C

XSON8U

plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3

× 2 × 0.5 mm

SOT996-2

74AUP2G32GM

−40 °C to +125 °C

XQFN8U

plastic extremely thin quad ﬂat package; no leads;

8 terminals; UTLP based; body 1.6

× 1.6 × 0.5 mm

SOT902-1

Table 2.

Marking codes

Type number

Marking code

74AUP2G32DC

p32

74AUP2G32GT

p32

74AUP2G32GD

p32

74AUP2G32GM

p32

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

001aah791

1A

1B

1Y

2A

2B

2Y

001aah792

≥ 1

mna166

B

A

Y

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74AUP2G32GM Datasheet(PDF) 2 Page - NXP Semiconductors

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