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74AUP2G240GT Datasheet(PDF) 3 Page - NXP Semiconductors

No. de pieza 74AUP2G240GT
Descripción Electrónicos  Low-power dual inverting buffer/line driver; 3-state
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP2G240GT Datasheet(HTML) 3 Page - NXP Semiconductors

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74AUP2G240_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 30 June 2009
3 of 20
NXP Semiconductors
74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
6.
Pinning information
6.1 Pinning
6.2 Pin description
Fig 3.
Pin configuration SOT765-1 (VSSOP8)
Fig 4.
Pin configuration SOT833-1 (XSON8)
74AUP2G240
1OE
VCC
1A
2OE
2Y
1Y
GND
2A
001aaf407
1
2
3
4
6
5
8
7
74AUP2G240
1Y
2OE
VCC
2A
2Y
1A
1OE
GND
001aaf408
36
27
18
45
Transparent top view
Fig 5.
Pin configuration SOT996-2 (XSON8U)
Fig 6.
Pin configuration SOT902-1 (XQFN8U)
001aaj919
74AUP2G240
Transparent top view
8
7
6
5
1
2
3
4
1OE
1A
2Y
GND
VCC
2OE
1Y
2A
001aaf409
1A
1Y
1OE
2Y
2OE
2A
Transparent top view
3
6
1
5
7
2
terminal 1
index area
74AUP2G240
Table 3.
Pin description
Symbol
Pin
Description
SOT765-1, SOT833-1 and SOT996-2
SOT902-1
1OE, 2OE
1, 7
7, 1
output enable input (active LOW)
1A, 2A
2, 5
6, 3
data input
GND
4
4
ground (0 V)
1Y, 2Y
6, 3
2, 5
data output
VCC
8
8
supply voltage


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