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74AUP2GU04GM Datasheet(PDF) 8 Page - NXP Semiconductors |
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74AUP2GU04GM Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 8 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 12. Waveforms [1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, set-up and hold times and pulse width RL =1MΩ. Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. The data input (nA) to output (nY) propagation delays mna344 tPHL tPLH VM VM VM VM nA input nY output GND VI VOH VOL Table 9. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times 001aac521 DUT RT VI VO VEXT VCC RL 5 k Ω CL G Table 10. Test data Supply voltage Load VEXT VCC CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k Ω or 1 MΩ open GND 2 × VCC |
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