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74HC3GU04 Datasheet(PDF) 6 Page - NXP Semiconductors |
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74HC3GU04 Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 16 page  74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 6 of 16 NXP Semiconductors 74HC3GU04 Inverter Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 6. Test circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open G Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC3GU04 GND to VCC ≤ 6 ns 50 pF 1 k Ω open |
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Descripción similar - 74HC3GU04 |
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