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74LVC1G07GM Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC1G07GM Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 14 page 74LVC1G07_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 17 July 2007 3 of 14 NXP Semiconductors 74LVC1G07 Buffer with open-drain output 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. Fig 4. Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 74LVC1G07 n.c. VCC A GND Y 001aab622 1 2 3 5 4 74LVC1G07 A 001aab623 n.c. GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 74LVC1G07 A 001aag422 n.c. GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description SOT353-1/SOT753 SOT886/SOT891 n.c. 1 1 not connected A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage Table 4. Function table[1] Input A Output Y LL HZ |
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