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74LVC2G38GD Datasheet(PDF) 7 Page - NXP Semiconductors |
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74LVC2G38GD Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 16 page 74LVC2G38_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 20 March 2009 7 of 16 NXP Semiconductors 74LVC2G38 Dual 2-input NAND gate; open drain 11. Dynamic characteristics [1] Typical values are measured at nominal VCC and at Tamb =25 °C. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(C L × VCC 2 × f o) = sum of outputs. 12. Waveforms Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max tPZL OFF-state to LOW propagation delay nA, nB to nY; see Figure 8 VCC = 1.65 V to 1.95 V 1.2 3.0 8.6 1.2 10.8 ns VCC = 2.3 V to 2.7 V 0.7 1.8 4.8 0.7 6.0 ns VCC = 2.7 V 0.7 2.5 4.4 0.7 5.5 ns VCC = 3.0 V to 3.6 V 0.7 2.1 4.1 0.7 5.2 ns VCC = 4.5 V to 5.5 V 0.5 1.5 3.3 0.5 4.2 ns tPLZ LOW to OFF-state propagation delay nA, nB to nY; see Figure 8 VCC = 1.65 V to 1.95 V 1.2 3.0 8.6 1.2 10.8 ns VCC = 2.3 V to 2.7 V 0.7 1.8 4.8 0.7 6.0 ns VCC = 2.7 V 0.7 2.5 4.4 0.7 5.5 ns VCC = 3.0 V to 3.6 V 0.7 2.1 4.1 0.7 5.2 ns VCC = 4.5 V to 5.5 V 0.5 1.5 3.3 0.5 4.2 ns CPD power dissipation capacitance per gate; VI = GND to VCC [2] -5 - - - pF Measurement points are given in Table 9 Fig 8. Inputs nA and nB to output nY propagation delay times mnb132 tPLZ VX nY output nA, nB input VI VCC VM VOL GND tPZL VM |
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