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74LVC2G240GM Datasheet(PDF) 1 Page - NXP Semiconductors

No. de pieza 74LVC2G240GM
Descripción Electrónicos  Dual inverting buffer/line driver; 3-state
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
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74LVC2G240GM Datasheet(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state
outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at
pins nOE causes the outputs to assume a high-impedance OFF-state. Schmitt trigger
action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G240 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing a damaging backflow current through the device when it is
powered down.
2.
Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °Cto+85 °C and −40 °C to +125 °C
74LVC2G240
Dual inverting buffer/line driver; 3-state
Rev. 04 — 29 February 2008
Product data sheet


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