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CS4226-BQ Datasheet(PDF) 24 Page - Cirrus Logic |
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CS4226-BQ Datasheet(HTML) 24 Page - Cirrus Logic |
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24 / 37 page  CS4226 24 DS188F4 3 REGISTER DESCRIPTION 3.1 Memory Address Pointer (MAP) MAP4-MAP0 Register Pointer INCR Auto Increment Control Bit 0 - No auto increment 1 - Auto increment on This register defaults to 01h. 3.2 Reserved Byte (00h) This byte is reserved for internal use and must be set to 00h for normal operation. This register defaults to 00h. 3.3 Clock Mode Byte (01h) CS2-CS0 Sets the source of the master clock. 0 - Crystal Oscillator or XTI at high frequency (PLL disabled) 1 - PLL driven by LRCKAUX at 1 Fs 2 - PLL driven by LRCK at 1 Fs 3 - PLL driven by XTI at 1 Fs 4 - PLL driven by RX1 data. This changes AUX port to S/PDIF port. 5 - PLL driven by RX2 data. This changes AUX port to S/PDIF port. 6 - PLL driven by RX3 data. This changes AUX port to S/PDIF port. 7 - PLL driven by RX4 data. This changes AUX port to S/PDIF port. CI1-CI0 Determines frequency of XTI when PLL is disabled (not used if CS ≠ 0) 0 - 256 Fs 1 - 384 Fs 2 - 512 Fs 3 - not used CO1-CO0 Sets CLKOUT frequency 0 - 256 Fs 1 - 384 Fs 2 - 512 Fs 3 - 1 Fs This register defaults to 01h. NOTE: If the sample rate on an input pin changes while using the PLL with RX1, RX2, RX3 or RX4, the PLL will not resynchronize to the new sample rate. You must either change input pins or change the Clock Mode Byte to something else and then change it back to the correct value. This will cause the PLL to resync. B7 B6 B5 B4 B3 B2 B1 B0 INCR 0 0 MAP4 MAP3 MAP2 MAP1 MAP0 B7 B6 B5 B4 B3 B2 B1 B0 0 CO1 CO0 CI1 CI0 CS2 CS1 CS0 |
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Descripción similar - CS4226-BQ |
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