N+1

N+2

N+6

t

CLKH

t

CLKL

N+3

N+4

N+5

t

DRY

t

DATA

Sample

N

T0158-02

Latency = 5 Clock Cycles

Dx_y_P

Dx_y_M

CLKM

CLKP

DRY_M

DRY_P

Sampling

Clock Input

Data Clock

Output

Output Data

O

O

O

O

O

O

O

E

E

E

E

E

E

E

N

N – 1

E = Even Bits = B0, B2, B4, B6, B8, B10, B12, B14

O = Odd Bits = B1, B3, B5, B7, B9, B11, B13, B15

Dx_y_P/M are LVDS outputs that have two bits per pair (EVEN and ODD). The values for x and y are 0_1, 2_3, 4_5, ... 14_15.

Aperture

Delay

t

a

ADS5484

ADS5485

TIMING INFORMATION

Figure 1. Timing Diagram

TIMING CHARACTERISTICS

(1)

unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

200

ps

Aperture jitter, rms

Internal jitter of the ADC

80

fs

Latency

5

cycles

Clock period

1e9/CLK

100

ns

CLK = max rated clock for that part

Clock pulse duration, high

0.5e9/CLK

50

ns

number

Clock pulse duration, low

0.5e9/CLK

50

ns

1500

1900

2300

ps

Zero crossing, 5-pF parasitic to GND

1400

1900

2400

ps

DATA to DRY skew

–500

0

500

ps

DRY/DATA rise time

500

ps

5-pF parasitic to GND

DRY/DATA fall time

500

ps

(1)

Timing parameters are assured by design or characterization, but not production tested.

(2)

delay.

Copyright © 2008–2009, Texas Instruments Incorporated

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