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ADS5485IRGCRG4 Datasheet(PDF) 9 Page - Texas Instruments

No. de pieza ADS5485IRGCRG4
Descripción Electrónicos  16-Bit, 170/200-MSPS Analog-to-Digital Converters
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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ADS5485IRGCRG4 Datasheet(HTML) 9 Page - Texas Instruments

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ADS5484
ADS5485
www.ti.com ............................................................................................................................................... SLAS610C – AUGUST 2008 – REVISED OCTOBER 2009
Table 2. PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
1, 2, 8, 14, 18,
AVDD5
5-V analog supply
24, 27, 30
9, 15, 19, 25,
AVDD3
3.3-V analog supply
28, 31
3, 7, 10, 13, 17,
AGND
20, 23, 26, 29,
Analog ground
32
DVDD3
42, 52, 63
3.3-V digital supply
DGND
41, 51, 64
Digital ground
NC
5, 6, 37-40
No connect - leave floating
INP, INM
11, 12
Differential analog inputs (P = plus = true, M = minus = complement)
CLKM, CLKP
21, 22
Differential clock inputs (P = plus = true, M = minus = complement)
Reference voltage input/output (1.2 V nominal). To use an external reference and to turn the internal
REF
4
reference off, pull both PDWNF and PDWNS to logic high (DVDD3). A 0.1-
μF capacitor to ground on
REF is recommended but not required.
Analog input common mode, output (3.1V), for use in applications that require use of the internally
VCM
16
generated common-mode. See the Applications section for more information on using VCM. A 0.1-
μF
capacitor to ground on VCM is recommended but not required.
External bias resistor for LVDS bias current, normally 10 k
Ω to GND to provide nominal 3.5-mA LVDS
LVDSB
33
current.
Light sleep power down, fast wake-up, logic high (DVDD3) = light sleep enabled (bandgap reference
PDWNF
34
remains on)
Deep sleep power down, slow wake-up, logic high (DVDD3) = deep sleep enabled (bandgap reference
PDWNS
35
is off)
DITHER
36
Dither enable, logic high (DVDD3) = dither enabled
DRY_P,
54, 53
Data ready signal (LVDS clock out) (P = plus = true, M = minus = complement)
DRY_M
D14_15_P,
62, 61
DDR LVDS output bits 14 then 15 (15 is MSB) (P = plus = true, M = minus = complement)
D14_15_M
DE_O_P,
43-50, 55-62
DDR LVDS output bits E (even) then O (odd) (P = plus = true, M = minus = complement)
DE_O_M
D0_1_P,
44, 43
DDR LVDS output bits 0 then 1 (0 is LSB) (P = plus = true, M = minus = complement)
D0_1_M
PowerPAD
65
Analog ground (exposed pad on bottom of package)
Copyright © 2008–2009, Texas Instruments Incorporated
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