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LM3S6730-IGZ25-A2 Datasheet(PDF) 11 Page - Texas Instruments |
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LM3S6730-IGZ25-A2 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 441 page  List of Registers System Control .............................................................................................................................. 59 Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 70 Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 72 Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 73 Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 74 Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 75 Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 76 Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 77 Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 78 Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 82 Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 83 Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 85 Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 86 Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 88 Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 89 Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 91 Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 93 Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 95 Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 97 Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 98 Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 99 Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 100 Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 102 Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 104 Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 106 Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 108 Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 110 Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 112 Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 113 Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 114 Internal Memory ........................................................................................................................... 116 Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 121 Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 122 Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 123 Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 125 Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 126 Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 127 Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 129 Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 130 Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 131 Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 132 Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 133 Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 134 Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 135 Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 136 11 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller |
Número de pieza similar - LM3S6730-IGZ25-A2 |
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Descripción similar - LM3S6730-IGZ25-A2 |
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