Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
TPS79533DCQG4 Datasheet(PDF) 2 Page - Texas Instruments |
|
|
TPS79533DCQG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 23 page www.ti.com ABSOLUTE MAXIMUM RATINGS DISSIPATION RATING TABLE TPS795xx SLVS350G – OCTOBER 2002 – REVISED JULY 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT VOUT(2) TPS795xxyyyz XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable). YYY is package designator. Z is package quantity. (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Output voltages from 1.3 V to 5.0 V in 100 mV increments are available; minimum order quantities may apply. Contact factory for details and availability. over operating temperature (unless otherwise noted)(1) VALUE VIN range – 0.3 V to 6 V VEN range –0.3 V to VIN + 0.3 V VOUT range 6 V Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation See Dissipation Rating Table Junction temperature range, TJ –40 °C to +150°C Storage temperature range, Tstg –65 °C to +150°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. PACKAGE BOARD RθJC RθJA SOT223 Low K(1) 15 °C/W 53 °C/W 3 x 3 SON High-K(2) 1.2 °C/W 40 °C/W (1) The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch (7.5 cm × 7.5cm), two-layer board with 2-ounce copper traces on top of the board. (2) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch (7,5-cm × 7,5-cm), multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. 2 Submit Documentation Feedback |
Número de pieza similar - TPS79533DCQG4 |
|
Descripción similar - TPS79533DCQG4 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |