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ADS5474IPFPG4 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS5474IPFPG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 38 page ADS5474 www.ti.com......................................................................................................................................................... SLAS525A – JULY 2007 – REVISED AUGUST 2008 Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. AIN 16 Differential input signal (positive) AIN 17 Differential input signal (negative) 3, 8, 13, 14, 19, 21, AVDD5 Analog power supply (5 V) 23, 25, 27, 31 Analog power supply (3.3 V) (Suggestion for ≤ 250 MSPS: leave option to connect to 5 V for AVDD3 35, 37, 39 ADS5440/ADS5444 13-bit compatibility) DVDD3 1, 51, 66 Digital and output driver power supply (3.3 V) 7, 9, 12, 15, 18, 20, AGND 22, 24, 26, 28, 30, Analog Ground 32, 34, 36, 38, 40 (Power Pad) (not numbered) Power Pad for thermal relief, also Analog Ground DGND 2, 52, 65 Digital Ground CLK 10 Differential input clock (positive). Conversion is initiated on rising edge, digital outputs on falling edge. CLK 11 Differential input clock (negative) D0, D0 48, 47 LVDS digital output pair, least significant bit (LSB) D1–D12, 49, 50, 53–64, LVDS digital output pairs D1–D12 67–76 D13, D13 78, 77 LVDS digital output pair, most significant bit (MSB) DRY, DRY 80, 79 Data ready LVDS output pair No connect (pins 4 and 5 should be left floating; pins 43 to 46 are possible future bit additions for this NC 4, 5, 43–46 pinout and therefore can be connected to a digital bus or left floating) Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale OVR, OVR 42, 41 range. Common-mode voltage output (3.1 V nominal). Commonly used in DC-coupled applications to set the input signal to the correct common-mode voltage. A 0.1 µF capacitor from VCM to AGND is VCM 29 recommended, but not required. (This pin is not used on the ADS5440, ADS5444, and ADS5463) Power-down (active high). Device is in sleep mode when PWD pin is logic HIGH. ADC converter is PWD 33 awake when PWD is logic LOW (grounded). (This pin is not used on the ADS5440, ADS5444, and ADS5463) Reference voltage input/output (2.4 V nominal). A 0.1 µF capacitor from VREF to AGND is VREF 6 recommended, but not required. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS5474 |
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