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MC908QY1ACPE Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc |
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MC908QY1ACPE Datasheet(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 200 page  Registers MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 49 ADIV[1:0] — ADC10 Clock Divider Bits ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK. Table 3-3 shows the available clock configurations. ADICLK — Input Clock Select Bit If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock source to generate the internal clock ADCK. If the alternate clock source is less than the minimum clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (fADCK) between the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed. 1 = The internal bus clock is selected as the input clock source 0 = The alternate clock source IS SELECTED MODE[1:0] — 10- or 8-Bit or Hardware Triggered Mode Selection These bits select 10- or 8-bit operation. The successive approximation converter generates a result that is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the transfer function to transition at the midpoint between the ideal code voltages, causing a quantization error of ± 1/2LSB. Reset returns 8-bit mode. 00 = 8-bit, right-justified, ADSCR software triggered mode enabled 01 = 10-bit, right-justified, ADSCR software triggered mode enabled 10 = Reserved 11 = 10-bit, right-justified, hardware triggered mode enabled ADLSMP — Long Sample Time Configuration This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption in continuous conversion mode if high conversion rates are not required. 1 = Long sample time (23.5 cycles) 0 = Short sample time (3.5 cycles) ACLKEN — Asynchronous Clock Source Enable This bit enables the asynchronous clock source as the input clock to generate the internal clock ADCK, and allows operation in stop mode. The asynchronous clock source will operate between 1 MHz and 2 MHz if ADLPC is clear, and between 0.5 MHz and 1 MHz if ADLPC is set. 1 = The asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion) 0 = ADICLK specifies the input clock source and conversions will not continue in stop mode Table 3-3. ADC10 Clock Divide Ratio ADIV1 ADIV0 Divide Ratio (ADIV) Clock Rate 0 0 1 Input clock ÷ 1 0 1 2 Input clock ÷ 2 1 0 4 Input clock ÷ 4 1 1 8 Input clock ÷ 8 |
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