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MC908QY2ACPE Datasheet(PDF) 58 Page - Freescale Semiconductor, Inc

No. de Pieza. MC908QY2ACPE
Descripción  M68HC08 Microcontrollers
Descarga  200 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC908QY2ACPE Datasheet(HTML) 58 Page - Freescale Semiconductor, Inc

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Configuration Register (CONFIG)
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
58
Freescale Semiconductor
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and VDD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
OSCENINSTOP— Oscillator Enable in Stop Mode Bit
OSCENINSTOP, when set, will allow the clock source to continue to generate clocks in stop mode.
This function can be used to keep the auto-wakeup running while the rest of the microcontroller stops.
When clear, the clock source is disabled when the microcontroller enters stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
RSTEN — RST Pin Function Selection
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE
The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will
leave this bit unaffected.
COPRS (Out of Stop Mode) — COP Reset Period Selection Bit
1 = COP reset short cycle = 8176
× BUSCLKX4
0 = COP reset long cycle = 262,128
× BUSCLKX4
COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in
CONFIG2 and external clock source
1 = Auto wakeup short cycle = 512
× (INTRCOSC or BUSCLKX2)
0 = Auto wakeup long cycle = 16,384
× (INTRCOSC or BUSCLKX2)
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
1 = LVI module resets disabled
0 = LVI module resets enabled
Bit 7
6
5
4
3
2
1
Bit 0
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVITRIP
SSREC
STOP
COPD
Write:
Reset:
000
0
U
000
POR:
000
0
0000
U = Unaffected
Figure 5-2. Configuration Register 1 (CONFIG1)


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