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MC908QT1AMPE Datasheet(Hoja de datos) 39 Page - Freescale Semiconductor, Inc

No. de Pieza. MC908QT1AMPE
Descripción  M68HC08 Microcontrollers
Descarga  200 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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 39 page
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Functional Description
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
Freescale Semiconductor
39
Figure 3-2. ADC10 Block Diagram
The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The
output of the input multiplexer (ADVIN) is converted by a successive approximation algorithm into a 10-bit
digital result. When the conversion is completed, the result is placed in the data registers (ADRH and
ADRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADRL. The conversion complete flag
is then set and an interrupt is generated if the interrupt has been enabled.
3.3.1 Clock Select and Divide Circuit
The clock select and divide circuit selects one of three clock sources and divides it by a configurable value
to generate the input clock to the converter (ADCK). The clock can be selected from one of the following
sources:
The asynchronous clock source (ACLK) — This clock source is generated from a dedicated clock
source which is enabled when the ADC10 is converting and the clock source is selected by setting
the ACLKEN bit. When the ADLPC bit is clear, this clock operates from 1–2 MHz; when ADLPC is
set it operates at 0.5–1 MHz. This clock is not disabled in STOP and allows conversions in stop
mode for lower noise operation.
Alternate Clock Source — This clock source is equal to the external oscillator clock or a four times
the bus clock. The alternate clock source is MCU specific, see 3.1 Introduction to determine source
and availability of this clock source option. This clock is selected when ADICLK and ACLKEN are
both low.
The bus clock — This clock source is equal to the bus frequency. This clock is selected when
ADICLK is high and ACLKEN is low.
Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If
the available clocks are too slow, the ADC10 will not perform according to specifications. If the available
AD0
ADn
VREFH
VREFL
ADVIN
CONTROL SEQUENCER
ADCK
BUS CLOCK
ALTERNATE CLOCK SOURCE
ACLK
ADSCR
DATA REGISTERS ADRH:ADRL
SAR CONVERTER
INTERRUPT
AIEN
COCO
1
2
1
2
MCU STOP
ADHWT
ADCLK
ACLKEN
ASYNC
CLOCK
GENERATOR
CLOCK
DIVIDE




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