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MC908QC8CDRE Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc

No. de Pieza. MC908QC8CDRE
Descripción  M68HC08 Microcontrollers
Descarga  274 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC908QC8CDRE Datasheet(HTML) 49 Page - Freescale Semiconductor, Inc

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Functional Description
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
Freescale Semiconductor
49
When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case
that the conversion was aborted by a reset, ADRH and ADRL return to their reset states.
Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive
state. In this state, all internal clocks and references are disabled. This state is entered asynchronously
and immediately upon aborting of a conversion.
3.3.3.4 Total Conversion Time
The total conversion time depends on many factors such as sample time, bus frequency, whether
ACLKEN is set, and synchronization time. The total conversion time is summarized in Table 3-1.
The maximum total conversion time for a single conversion or the first conversion in continuous
conversion mode is determined by the clock source chosen and the divide ratio selected. The clock
source is selectable by ADICLK and ACLKEN, and the divide ratio is specified by ADIV. For example, if
the alternative clock source is 16 MHz and is selected as the input clock source, the input clock
divide-by-8 ratio is selected and the bus frequency is 4 MHz, then the conversion time for a single 10-bit
conversion is:
NOTE
The ADCK frequency must be between fADCK minimum and fADCK
maximum to meet A/D specifications.
Table 3-1. Total Conversion Time versus Control Conditions
Conversion Mode
ACLKEN
Maximum Conversion Time
8-Bit Mode (short sample — ADLSMP = 0):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (fBus ≥ fADCK)
0
1
X
18 ADCK + 3 bus clock
18 ADCK + 3 bus clock + 5
µs
16 ADCK
8-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (fBus ≥ fADCK)
0
1
X
38 ADCK + 3 bus clock
38 ADCK + 3 bus clock + 5
µs
36 ADCK
10-Bit Mode (short sample — ADLSMP = 0):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (fBus ≥ fADCK)
0
1
X
21 ADCK + 3 bus clock
21 ADCK + 3 bus clock + 5
µs
19 ADCK
10-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (fBus ≥ fADCK)
0
1
X
41 ADCK + 3 bus clock
41 ADCK + 3 bus clock + 5
µs
39 ADCK
21 ADCK cycles
Conversion time =
16 MHz/8
Number of bus cycles = 11.25
µs x 4 MHz = 45 cycles
3 bus cycles
4 MHz
+
= 11.25
µs


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