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MC908QC8CDRE Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc

No. de Pieza. MC908QC8CDRE
Descripción  M68HC08 Microcontrollers
Descarga  274 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC908QC8CDRE Datasheet(HTML) 60 Page - Freescale Semiconductor, Inc

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Configuration Registers (CONFIG1 and CONFIG2)
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
60
Freescale Semiconductor
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and VDD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
TIM2POS — TIM2 Position Bit
TIM2POS is used to reposition the timer channels for TIM2 to a different pair of pins. This allows the
user to free up one of the communication ports based on application needs.
1 = TIM2 timer channel pins share PTB4 and PTB5
0 = TIM2 timer channel pins share PTB1 and PTB2
ESCIBDSRC — ESCI Baud Rate Clock Source Bit
ESCIBDSRC controls the clock source used for the ESCI. The setting of the bit affects the frequency
at which the ESCI operates.
1 = Internal data bus clock used as clock source for ESCI
0 = BUSCLKX4 used as clock source for ESCI
OSCENINSTOP— Oscillator Enable in Stop Mode Bit
OSCENINSTOP, when set, will allow the clock source to continue to generate clocks in stop mode.
This function can be used to keep the periodic wakeup running while the rest of the microcontroller
stops. When clear, the clock source is disabled when the microcontroller enters stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
RSTEN — RST Pin Function Selection
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE
The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will
leave this bit unaffected.
COPRS — COP Reset Period Selection Bit
1 = COP reset short cycle = 8176
× BUSCLKX4
0 = COP reset long cycle = 262,128
× BUSCLKX4
Bit 7
6
5
4
3
2
1
Bit 0
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVITRIP
SSREC
STOP
COPD
Write:
Reset:
000
0
U
000
POR:
0
0
0
0
0000
U = Unaffected
Figure 4-2. Configuration Register 1 (CONFIG1)


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