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MC908QC8CDRE Datasheet(PDF) 78 Page - Freescale Semiconductor, Inc

No. de Pieza. MC908QC8CDRE
Descripción  M68HC08 Microcontrollers
Descarga  274 Pages
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Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC908QC8CDRE Datasheet(HTML) 78 Page - Freescale Semiconductor, Inc

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Table 6-2. Opcode Map
Bit Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
INH
INH
IX1
SP1
IX
INH
INH
IMM
DIR
EXT
IX2
SP2
IX1
SP1
IX
0
1
23456
9E6
789
A
B
C
D
9ED
E
9EE
F
0
5
BRSET0
3
DIR
4
BSET0
2
DIR
3
BRA
2
REL
4
NEG
2
DIR
1
NEGA
1
INH
1
NEGX
1
INH
4
NEG
2
IX1
5
NEG
3
SP1
3
NEG
1IX
7
RTI
1
INH
3
BGE
2
REL
2
SUB
2
IMM
3
SUB
2
DIR
4
SUB
3
EXT
4
SUB
3
IX2
5
SUB
4
SP2
3
SUB
2
IX1
4
SUB
3
SP1
2
SUB
1IX
1
5
BRCLR0
3
DIR
4
BCLR0
2
DIR
3
BRN
2
REL
5
CBEQ
3
DIR
4
CBEQA
3
IMM
4
CBEQX
3
IMM
5
CBEQ
3 IX1+
6
CBEQ
4
SP1
4
CBEQ
2
IX+
4
RTS
1
INH
3
BLT
2
REL
2
CMP
2
IMM
3
CMP
2
DIR
4
CMP
3
EXT
4
CMP
3
IX2
5
CMP
4
SP2
3
CMP
2
IX1
4
CMP
3
SP1
2
CMP
1IX
2
5
BRSET1
3
DIR
4
BSET1
2
DIR
3
BHI
2
REL
5
MUL
1
INH
7
DIV
1
INH
3
NSA
1
INH
2
DAA
1
INH
3
BGT
2
REL
2
SBC
2
IMM
3
SBC
2
DIR
4
SBC
3
EXT
4
SBC
3
IX2
5
SBC
4
SP2
3
SBC
2
IX1
4
SBC
3
SP1
2
SBC
1IX
3
5
BRCLR1
3
DIR
4
BCLR1
2
DIR
3
BLS
2
REL
4
COM
2
DIR
1
COMA
1
INH
1
COMX
1
INH
4
COM
2
IX1
5
COM
3
SP1
3
COM
1IX
9
SWI
1
INH
3
BLE
2
REL
2
CPX
2
IMM
3
CPX
2
DIR
4
CPX
3
EXT
4
CPX
3
IX2
5
CPX
4
SP2
3
CPX
2
IX1
4
CPX
3
SP1
2
CPX
1IX
4
5
BRSET2
3
DIR
4
BSET2
2
DIR
3
BCC
2
REL
4
LSR
2
DIR
1
LSRA
1
INH
1
LSRX
1
INH
4
LSR
2
IX1
5
LSR
3
SP1
3
LSR
1IX
2
TAP
1
INH
2
TXS
1
INH
2
AND
2
IMM
3
AND
2
DIR
4
AND
3
EXT
4
AND
3
IX2
5
AND
4
SP2
3
AND
2
IX1
4
AND
3
SP1
2
AND
1IX
5
5
BRCLR2
3
DIR
4
BCLR2
2
DIR
3
BCS
2
REL
4
STHX
2
DIR
3
LDHX
3
IMM
4
LDHX
2
DIR
3
CPHX
3
IMM
4
CPHX
2
DIR
1
TPA
1
INH
2
TSX
1
INH
2
BIT
2
IMM
3
BIT
2
DIR
4
BIT
3
EXT
4
BIT
3
IX2
5
BIT
4
SP2
3
BIT
2
IX1
4
BIT
3
SP1
2
BIT
1IX
6
5
BRSET3
3
DIR
4
BSET3
2
DIR
3
BNE
2
REL
4
ROR
2
DIR
1
RORA
1
INH
1
RORX
1
INH
4
ROR
2
IX1
5
ROR
3
SP1
3
ROR
1IX
2
PULA
1
INH
2
LDA
2
IMM
3
LDA
2
DIR
4
LDA
3
EXT
4
LDA
3
IX2
5
LDA
4
SP2
3
LDA
2
IX1
4
LDA
3
SP1
2
LDA
1IX
7
5
BRCLR3
3
DIR
4
BCLR3
2
DIR
3
BEQ
2
REL
4
ASR
2
DIR
1
ASRA
1
INH
1
ASRX
1
INH
4
ASR
2
IX1
5
ASR
3
SP1
3
ASR
1IX
2
PSHA
1
INH
1
TAX
1
INH
2
AIS
2
IMM
3
STA
2
DIR
4
STA
3
EXT
4
STA
3
IX2
5
STA
4
SP2
3
STA
2
IX1
4
STA
3
SP1
2
STA
1IX
8
5
BRSET4
3
DIR
4
BSET4
2
DIR
3
BHCC
2
REL
4
LSL
2
DIR
1
LSLA
1
INH
1
LSLX
1
INH
4
LSL
2
IX1
5
LSL
3
SP1
3
LSL
1IX
2
PULX
1
INH
1
CLC
1
INH
2
EOR
2
IMM
3
EOR
2
DIR
4
EOR
3
EXT
4
EOR
3
IX2
5
EOR
4
SP2
3
EOR
2
IX1
4
EOR
3
SP1
2
EOR
1IX
9
5
BRCLR4
3
DIR
4
BCLR4
2
DIR
3
BHCS
2
REL
4
ROL
2
DIR
1
ROLA
1
INH
1
ROLX
1
INH
4
ROL
2
IX1
5
ROL
3
SP1
3
ROL
1IX
2
PSHX
1
INH
1
SEC
1
INH
2
ADC
2
IMM
3
ADC
2
DIR
4
ADC
3
EXT
4
ADC
3
IX2
5
ADC
4
SP2
3
ADC
2
IX1
4
ADC
3
SP1
2
ADC
1IX
A
5
BRSET5
3
DIR
4
BSET5
2
DIR
3
BPL
2
REL
4
DEC
2
DIR
1
DECA
1
INH
1
DECX
1
INH
4
DEC
2
IX1
5
DEC
3
SP1
3
DEC
1IX
2
PULH
1
INH
2
CLI
1
INH
2
ORA
2
IMM
3
ORA
2
DIR
4
ORA
3
EXT
4
ORA
3
IX2
5
ORA
4
SP2
3
ORA
2
IX1
4
ORA
3
SP1
2
ORA
1IX
B
5
BRCLR5
3
DIR
4
BCLR5
2
DIR
3
BMI
2
REL
5
DBNZ
3
DIR
3
DBNZA
2
INH
3
DBNZX
2
INH
5
DBNZ
3
IX1
6
DBNZ
4
SP1
4
DBNZ
2IX
2
PSHH
1
INH
2
SEI
1
INH
2
ADD
2
IMM
3
ADD
2
DIR
4
ADD
3
EXT
4
ADD
3
IX2
5
ADD
4
SP2
3
ADD
2
IX1
4
ADD
3
SP1
2
ADD
1IX
C
5
BRSET6
3
DIR
4
BSET6
2
DIR
3
BMC
2
REL
4
INC
2
DIR
1
INCA
1
INH
1
INCX
1
INH
4
INC
2
IX1
5
INC
3
SP1
3
INC
1IX
1
CLRH
1
INH
1
RSP
1
INH
2
JMP
2
DIR
3
JMP
3
EXT
4
JMP
3
IX2
3
JMP
2
IX1
2
JMP
1IX
D
5
BRCLR6
3
DIR
4
BCLR6
2
DIR
3
BMS
2
REL
3
TST
2
DIR
1
TSTA
1
INH
1
TSTX
1
INH
3
TST
2
IX1
4
TST
3
SP1
2
TST
1IX
1
NOP
1
INH
4
BSR
2
REL
4
JSR
2
DIR
5
JSR
3
EXT
6
JSR
3
IX2
5
JSR
2
IX1
4
JSR
1IX
E
5
BRSET7
3
DIR
4
BSET7
2
DIR
3
BIL
2
REL
5
MOV
3DD
4
MOV
2 DIX+
4
MOV
3
IMD
4
MOV
2 IX+D
1
STOP
1
INH
*
2
LDX
2
IMM
3
LDX
2
DIR
4
LDX
3
EXT
4
LDX
3
IX2
5
LDX
4
SP2
3
LDX
2
IX1
4
LDX
3
SP1
2
LDX
1IX
F
5
BRCLR7
3
DIR
4
BCLR7
2
DIR
3
BIH
2
REL
3
CLR
2
DIR
1
CLRA
1
INH
1
CLRX
1
INH
3
CLR
2
IX1
4
CLR
3
SP1
2
CLR
1IX
1
WAIT
1
INH
1
TXA
1
INH
2
AIX
2
IMM
3
STX
2
DIR
4
STX
3
EXT
4
STX
3
IX2
5
STX
4
SP2
3
STX
2
IX1
4
STX
3
SP1
2
STX
1IX
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
IMM Immediate
IX
Indexed, No Offset
SP2 Stack Pointer, 16-Bit Offset
DIR Direct
IX1
Indexed, 8-Bit Offset
IX+
Indexed, No Offset with
EXT Extended
IX2
Indexed, 16-Bit Offset
Post Increment
DD
Direct-Direct
IMD Immediate-Direct
IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct
DIX+ Direct-Indexed
Post Increment
*Pre-byte for stack pointer indexed instructions
0
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5
BRSET0
3
DIR
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
MSB
LSB
MSB
LSB


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