Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼

Delete All
ON OFF
ALLDATASHEET.ES

X  

Preview PDF Download HTML

MC908QT2ACDWE Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc

No. de Pieza. MC908QT2ACDWE
Descripción  M68HC08 Microcontrollers
Descarga  200 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo 

MC908QT2ACDWE Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc

Zoom Inzoom in Zoom Outzoom out
 47 / 200 page
background image
Registers
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
Freescale Semiconductor
47
If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th
of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in
long-sample mode (ADLSMP = 1).
When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADSCR
is written (assuming the ADCH[4:0] bits do not decode all 1s).
1 = Continuous conversion following a write to ADSCR
0 = One conversion following a write to ADSCR
ADCH[4:0] — Channel Select Bits
The ADCH[4:0] bits form a 5-bit field that is used to select one of the input channels. The input
channels are detailed in Table 3-2. The successive approximation converter subsystem is turned off
when the channel select bits are all set to 1. This feature allows explicit disabling of the ADC10 and
isolation of the input channel from the I/O pad. Terminating continuous conversion mode this way will
prevent an additional, single conversion from being performed. It is not necessary to set the channel
select bits to all 1s to place the ADC10 in a low-power state, however, because the module is
automatically placed in a low-power state when a conversion completes.
3.8.2 ADC10 Result High Register (ADRH)
This register holds the MSBs of the result and is updated each time a conversion completes. All other bits
read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the
result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then
the intermediate conversion result will be lost. In 8-bit mode, this register contains no interlocking with
ADRL.
Table 3-2. Input Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select(1)
1. If any unused or reserved channels are selected, the resulting conversion will
be unknown.
00000
AD0
00001
AD1
00010
AD2
00011
AD3
00100
AD4
00101
AD5
00110
Unused
Continuing through
Unused
11001
Unused
11010
BANDGAP REF(2)
2. Requires LVI to be powered (LVIPWRD =0, in CONFIG1)
11011
Reserved
11100
Reserved
11101
VREFH
11110
VREFL
11111
Low-power state


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Enlace URL




Privacy Policy
ALLDATASHEET.ES
Does ALLDATASHEET help your business so far?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn