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MC908QT4DWE Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc |
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MC908QT4DWE Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc |
47 / 168 page Input/Output Registers MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor 47 3.7.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. 3.7.3 ADC Input Clock Register This register selects the clock frequency for the ADC. ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock frequency should be set between fADIC(MIN) and fADIC(MAX). The analog input level should remain stable for the entire conversion time (maximum = 17 ADC clock cycles). Address: $003E Bit 7 654321 Bit 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: Reset: Indeterminate after reset = Unimplemented Figure 3-4. ADC Data Register (ADR) Address: $003F Bit 7 654321 Bit 0 Read: ADIV2 ADIV1 ADIV0 00000 Write: Reset: 00000000 = Unimplemented Figure 3-5. ADC Input Clock Register (ADICLK) Table 3-2. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 Bus clock ÷ 1 0 0 1 Bus clock ÷ 2 0 1 0 Bus clock ÷ 4 0 1 1 Bus clock ÷ 8 1 X X Bus clock ÷ 16 X = don’t care |
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