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MC908QY2DTE Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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MC908QY2DTE Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 168 page MC68HC908QY/QT Family Data Sheet, Rev. 6 Freescale Semiconductor 5 August, 2003 1.0 Reformatted to meet latest M68HC08 documentation standards N/A Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt module and TCLK pin designator. 20 Figure 1-2. MCU Pin Assignments — Added TCLK pin designator. 21 Table 1-2. Pin Functions — Added TCLK pin description. 22 Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to add TCLK. 23 Figure 2-1. Memory Map — Corrected names for the IRQ status and control register (INTSCR) bits 3–0. 26 3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock prescaler bits. 47 4.3 Functional Description — Updated periodic wakeup request values. 51 Figure 6-1. COP Block Diagram — Reworked for clarity 59 Chapter 8 External Interrupt (IRQ) — Corrected bit names for MODE, IRQF, ACK, and IMASK 77–79 Chapter 14 Timer Interface Module (TIM) — Added TCLK function. 131–139 15.3 Monitor Module (MON) — Updated with additional data. 147 Chapter 16 Electrical Specifications — Updated with additional data. 169–173 October, 2003 2.0 Figure 2-2. Control, Status, and Data Registers — Deleted unimplemented areas from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available. Also corrected $FFBF designation from unimplemented to reserved. 27 Figure 6-1. COP Block Diagram — Reworked for clarity 59 6.3.2 STOP Instruction — Added subsection 60 13.4.2 Active Resets from Internal Sources — Reworked notes for clarity. 111 Table 13-2. Reset Recovery Timing — Replaced previous table with new information. 112 Chapter 14 Timer Interface Module (TIM) — Updated with additional data. 131 Figure 15-3. Break I/O Register Summary — Corrected bit designators for the BRKAR register 143 15.3 Monitor Module (MON) — Clarified seventh bullet. 147 Table 17-1. MC Order Numbers — Corrected temperature and package designators. 175 January, 2004 3.0 Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the FLASH Block Protect Register at address location $FFBE and the Internal Oscillator Trim Value at $FFC0. 32 Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for clarity. 38 Revision History (Sheet 2 of 3) Date Revision Level Description Page Number(s) |
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