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PIC18F1XK22 Datasheet(PDF) 73 Page - Microchip Technology |
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PIC18F1XK22 Datasheet(HTML) 73 Page - Microchip Technology |
73 / 388 page 2010 Microchip Technology Inc. Preliminary DS41365D-page 73 PIC18F1XK22/LF1XK22 REGISTER 7-7: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 OSCFIE C1IE C2IE EEIE BCLIE —TMR3IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 =Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 C2IE: Comparator C2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 =Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 =Disabled bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 =Disabled bit 0 Unimplemented: Read as ‘0’ |
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