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MC9S12B128VPVM Datasheet(PDF) 11 Page - Motorola, Inc

No. de pieza MC9S12B128VPVM
Descripción Electrónicos  Covers also preliminary MC9S12B64 using MC9S12B128 die
Download  132 Pages
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Fabricante Electrónico  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC9S12B128VPVM Datasheet(HTML) 11 Page - Motorola, Inc

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Device User Guide —9S12B128DGV1/D V01.13
11
List of Figures
Figure 0-1
Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 1-1
MC9S12B128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 1-2
MC9S12B128 Memory Map out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 1-3
MC9S12B64 using MC9S12B128 die Memory Map out of Reset . . . . . . . . . . . .30
Figure 2-1
Pin Assignments in 112-pin LQFP for MC9S12B128 . . . . . . . . . . . . . . . . . . . . .50
Figure 2-2
Pin Assignments in 80-pin QFP for MC9S12B128 . . . . . . . . . . . . . . . . . . . . . . .51
Figure 2-3
PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 2-4
Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 2-5
Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 2-6
External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 3-1
Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Figure 21-1 Recommended PCB Layout 112LQFP Colpitts Oscillator. . . . . . . . . . . . . . . . . .77
Figure 21-2 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .78
Figure 21-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .79
Figure 21-4 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .80
Figure A-1
ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure A-2
Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure A-3
VREG_3V3 - Chip Power-up and Voltage Drops (not scaled). . . . . . . . . . . . . 106
Figure A-4
Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure A-5
Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-6
Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-7
SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure A-8
SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure A-9
SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure A-10 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure A-11 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure B-1
112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 128
Figure B-2
80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . . . 129


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