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PIC16F785 Datasheet(PDF) 91 Page - Microchip Technology |
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PIC16F785 Datasheet(HTML) 91 Page - Microchip Technology |
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91 / 206 page  © 2008 Microchip Technology Inc. DS41249E-page 89 PIC16F785/HV785 12.4 Effects of Reset A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged. 12.5 Use of the CCP Trigger An A/D conversion can be started by the “special event trigger” of the CCP module. This requires that the CCP1M3:CCP1M0 bits of the CCP1CON Register be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter. See Section 8.0 “Capture/Compare/PWM (CCP) Module” for more information. TABLE 12-3: SUMMARY OF A/D REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---- ADRESH Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result xxxx xxxx uuuu uuuu ADRESL Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result xxxx xxxx uuuu uuuu ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 ANSEL1 — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module. |
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