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SMJ320C6713BGNZA20EP Datasheet(PDF) 2 Page - Texas Instruments

No. de Pieza. SMJ320C6713BGNZA20EP
Descripción  FLOATING-POINT DIGITAL SIGNAL PROCESSORS
Descarga  131 Pages
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Fabricante  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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SMJ320C6713BGNZA20EP Datasheet(HTML) 2 Page - Texas Instruments

 
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SM320C6713-EP
SM320C6713B-EP
SGUS049I – AUGUST 2003 – REVISED SEPTEMBER 2009
www.ti.com
Contents
1
FEATURES
......................................................................................................................... 9
2
SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
..................................... 10
3
DEVICE INFORMATION
...................................................................................................... 11
3.1
Description
................................................................................................................. 14
3.2
Device Characteristics
.................................................................................................... 16
3.3
Functional Block and CPU (DSP Core) Diagram
..................................................................... 17
4
OVERVIEW
....................................................................................................................... 18
4.1
CPU (DSP Core) Description
............................................................................................ 18
4.2
Memory Map Summary
................................................................................................... 19
4.3
L2 Memory Structure Expanded
......................................................................................... 21
4.4
Peripheral Register Descriptions
........................................................................................ 22
4.5
Signal Groups Description
................................................................................................ 30
5
DEVICE CONFIGURATIONS
................................................................................................ 35
5.1
Device Configurations at Device Reset
................................................................................. 35
5.2
Peripheral Pin Selection at Device Reset
.............................................................................. 36
5.3
Peripheral Selection/Device Configurations Via the DEVCFG Control Register
.................................. 36
5.4
Multiplexed Pins
........................................................................................................... 37
5.5
Configuration Examples
.................................................................................................. 41
5.6
Debugging Considerations
............................................................................................... 47
6
TERMINAL FUNCTIONS
...................................................................................................... 47
6.1
Development Support
..................................................................................................... 54
6.2
Device and Development-Support Tool Nomenclature
............................................................... 55
6.2.1
Device Development Evolutionary Flow
..................................................................... 55
6.2.2
Support Tool Development Evolutionary Flow
.............................................................. 55
6.3
Ordering Nomenclature
................................................................................................... 56
6.4
Documentation Support
................................................................................................... 56
7
REGISTER INFORMATION
.................................................................................................. 58
7.1
CPU Control Status Register (CSR) Description
...................................................................... 58
7.2
Cache Configuration (CCFG) Register Description (13B)
........................................................... 59
7.3
Interrupts and Interrupt Selector
......................................................................................... 60
7.4
External Interrupt Sources
............................................................................................... 62
7.5
EDMA Module and EDMA Selector
..................................................................................... 63
8
PLL and PLL Controller
...................................................................................................... 67
8.1
PLL Registers
.............................................................................................................. 68
9
MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS
............................................. 74
9.1
McASP Block Diagram
.................................................................................................... 74
9.2
Multichannel Time Division Multiplexed (TDM) Synchronous Transfer Mode
..................................... 76
9.3
Burst Transfer Mode
...................................................................................................... 76
9.4
Supported Bit Stream Formats for TDM and Burst Transfer Modes
................................................ 77
9.5
Digital Audio Interface Transmitter (DIT) Transfer Mode (Transmitter Only)
...................................... 77
9.6
McASP Flexible Clock Generators
...................................................................................... 78
9.7
McASP Error Handling and Management
.............................................................................. 78
9.8
McASP Interrupts and EDMA Events
................................................................................... 79
9.9
I
2C
........................................................................................................................... 79
10
LOGIC AND POWER SUPPLY
.............................................................................................. 81
2
Contents
Copyright © 2003–2009, Texas Instruments Incorporated


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