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CAT522LI-T2 Datasheet(PDF) 6 Page - ON Semiconductor |
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CAT522LI-T2 Datasheet(HTML) 6 Page - ON Semiconductor |
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6 / 15 page  CAT522 Not Recommended for New Design Doc. No. MD-2004 Rev. I 6 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice PIN DESCRIPTION Pin Name Function 1 VDD Power supply positive 2 CLK Clock input pin 3 RDY/BSY ¯¯¯¯ Ready/Busy output 4 CS Chip select 5 DI Serial data input pin 6 DO Serial data output pin 7 PROG EEPROM Programming Enable Input 8 GND Power supply ground 9 VREFL1 Minimum DPP1 output voltage 10 VREFL2 Minimum DPP2 output voltage 11 VOUT2 DPP2 output 12 VOUT1 DPP1 output 13 VREFH2 Maximum DPP2 output voltage 14 VREFH1 Maximum DPP1 output voltage DPP addressing is as follows: DPP OUTPUT A0 A1 VOUT1 0 1 VOUT2 1 1 DEVICE OPERATION The CAT522 is a dual 8-bit configured digitally programmable potentiometer (DPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT522 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT522’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control regis– ters will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT522’s clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not neces– sary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. |
Número de pieza similar - CAT522LI-T2 |
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Descripción similar - CAT522LI-T2 |
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