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STE100P Datasheet(Hoja de datos) 4 Page - STMicroelectronics

No. de Pieza. STE100P
Descripción  10/100 FAST ETHERNET 3.3V TRANSCEIVER
Descarga  31 Pages
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Fabricante  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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STE100P
4/31
52
tx_er
I
Transmit Coding Error. The MAC asserts this input when an error has occurred
in the transmit data stream. When the STE100P is operating at 100 Mbps, the
STE100P responds by sending invalid code symbols on the line. In Symbol (5B)
Mode this pin functions as txd4.
51
43
44
46
47
rxd4
rxd3
rxd2
rxd1
rxd0
O
Receive Data. The STE100P drives received data on these outputs, synchro-
nous to rx_clk.
rxd4 is driven only in Symbol (5B) Mode.
48
rx_dv
O
Receive Data Valid. The STE100P asserts This signal when it drives valid data
on rxd. This output is synchronous to rx_clk.
51
rx_er
O
Receive Error. The STE100P asserts this output when it receives invalid sym-
bols from the network. This signal is synchronous to rx_clk. In Symbol (5B) Mode
this pin functions as rxd4.
49
rx_clk
O
Receive Clock. This continuous clock provides reference for rxd, rx_dv, and
rx_er signals. Refer to the Clock Requirements discussion in the Functional
Description section.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
59
col
O
Collision Detected. The STE100P asserts this output when detecting a collision.
This output remains High for the duration of the collision. This signal is asynchro-
nous and inactive during full-duplex operation.
60
crs
O
Carrier Sense. During half-duplex operation (PR0:8=0), the STE100P asserts
this output when either transmit or receive medium is non idle. During full duplex
operation (PR0:8=1), crs is asserted only when the receive medium is non-idle.
MII Control Interface
42
mdc
I
Management Data Clock. Clock for the mdio serial data channel. Maximum
frequency is 2.5 MHz.
41
mdio
I/O
Management Data Input/Output, Bi-directional serial data channel for PHY
communication.
61
mdint
OD
Management Data Interrupt. When any bit in PR18 = 1, an active High output
on this pin indicates status change in the corresponding bits in PR17.
Interrupt is cleared by reading Register PR17. Requires MDC edge to output.
Physical (Twisted Pair) Interface
12
x1
I
25 MHz reference clock input. When an external 25 MHz crystal is used, this pin
will be connected to one terminal of it. If an external 25 MHz clock source of
oscillator is used, then this pin will be the input pin of it.
11
x2
O
25 MHz reference clock output. When an external 25MHz crystal is used, this pin
will be connected to another terminal of if. If an external clock source is used,
then this pin should be left open.
21
23
txp
txn
O
The differential Transmit outputs of 100Base-TX or 10Base-T, these pins directly
output to the transformer.
19
18
rxp
rxn
I
The differential Receive inputs of 100Base-TX or 10Base-T, these pins directly
input from the transformer.
Table 2. Pin Description (continued)
Pin No.
Name
Type
Description




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