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CAT93C57LA-GT3E Datasheet(PDF) 5 Page - ON Semiconductor |
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CAT93C57LA-GT3E Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 17 page CAT93C56, CAT93C57 http://onsemi.com 5 Table 9. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50 ns Input Pulse Voltages 0.4 V to 2.4 V 4.5 V v VCC v 5.5 V Timing Reference Voltages 0.8 V, 2.0 V 4.5 V v VCC v 5.5 V Input Pulse Voltages 0.2 VCC to 0.7 VCC 1.8 V v VCC v 4.5 V Timing Reference Voltages 0.5 VCC 1.8 V v VCC v 4.5 V Output Load Current Source IOLmax/IOHmax; CL=100 pF Device Operation The CAT93C56/57 is a 2048−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C56/57 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 10−bit instructions for 93C57 or seven 11−bit instructions for 93C56 control the reading, writing and erase operations of the device. When organized as X8, seven 11−bit instructions for 93C57 or seven 12−bit instructions for 93C56 control the reading, writing and erase operations of the device. The CAT93C56/57 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The serial communication protocol follows the timing shown in Figure 2. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. SK DI CS DO VALID VALID DATA VALID Figure 2. Synchronous Data Timing tCSS tSKHI tSKLOW tDIS tDIS tDIH tCSH tCSMN tPD0, tPD1 |
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