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CAT93C56LE-1.8T3E Datasheet(PDF) 4 Page - ON Semiconductor

No. de pieza CAT93C56LE-1.8T3E
Descripción Electrónicos  2-Kb Microwire Serial CMOS EEPROM
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
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CAT93C56LE-1.8T3E Datasheet(HTML) 4 Page - ON Semiconductor

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CAT93C56, CAT93C57
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Table 6. A.C. CHARACTERISTICS (Note 5), CAT93C56, Die Rev. G – New Product
(VCC = +1.8V to +5.5V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Limits
Units
Min
Max
tCSS
CS Setup Time
50
ns
tCSH
CS Hold Time
0
ns
tDIS
DI Setup Time
100
ns
tDIH
DI Hold Time
100
ns
tPD1
Output Delay to 1
0.25
ms
tPD0
Output Delay to 0
0.25
ms
tHZ (Note 6)
Output Delay to High−Z
100
ns
tEW
Program/Erase Pulse Width
5
ms
tCSMIN
Minimum CS Low Time
0.25
ms
tSKHI
Minimum SK High Time
0.25
ms
tSKLOW
Minimum SK Low Time
0.25
ms
tSV
Output Delay to Status Valid
0.25
ms
SKMAX
Maximum Clock Frequency
DC
2000
kHz
Table 7. A.C. CHARACTERISTICS (Note 5), CAT93C56/57, Die Rev. E – Mature Product
(CAT93C56 Rev. E − NOT RECOMMENDED FOR NEW DESIGNS)
Symbol
Parameter
Limits
Units
VCC = 1.8 V − 5.5 V
VCC = 2.5 V − 5.5 V
VCC = 4.5 V − 5.5 V
Min
Max
Min
Max
Min
Max
tCSS
CS Setup Time
200
100
50
ns
tCSH
CS Hold Time
0
0
0
ns
tDIS
DI Setup Time
400
200
100
ns
tDIH
DI Hold Time
400
200
100
ns
tPD1
Output Delay to 1
1
0.5
0.25
ms
tPD0
Output Delay to 0
1
0.5
0.25
ms
tHZ
(Note 6)
Output Delay to High−Z
400
200
100
ns
tEW
Program/Erase Pulse Width
10
10
10
ms
tCSMIN
Minimum CS Low Time
1
0.5
0.25
ms
tSKHI
Minimum SK High Time
1
0.5
0.25
ms
tSKLOW
Minimum SK Low Time
1
0.5
0.25
ms
tSV
Output Delay to Status Valid
1
0.5
0.25
ms
SKMAX
Maximum Clock Frequency
DC
250
DC
500
DC
1000
kHz
Table 8. POWER−UP TIMING (Notes 6 and 7)
Symbol
Parameter
Max
Units
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.


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