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CAT130169LWI-GT3 Datasheet(PDF) 9 Page - ON Semiconductor |
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CAT130169LWI-GT3 Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 14 page CAT130xx © 2008 SCILLC. All rights reserved. 9 Doc. No. MD-1121 Rev. B Characteristics subject to change without notice Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN (Figure 7). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT130xx can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase All Upon receiving an ERAL command (Figure 8), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT130xx can be determi– ned by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Figure 7. Erase Instruction Timing Figure 8. ERAL Instruction Timing SK CS DI DO STANDBY HIGH-Z HIGH-Z 1 AN AN-1 BUSY READY STATUS VERIFY tSV tHZ tEW tCS 11 A0 SK CS DI DO STANDBY tCS HIGH-Z HIGH-Z 10 1 BUSY READY STATUS VERIFY tSV tHZ tEW 00 |
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