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MC14LC5003FU Datasheet(PDF) 9 Page - Motorola, Inc |
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MC14LC5003FU Datasheet(HTML) 9 Page - Motorola, Inc |
9 / 17 page 3–11 MC14LC5002 • MC14LC5003 • MC14LC5004 MOTOROLA PIN DESCRIPTIONS A0, A1,A2 for MC14LC5003/5004 A0/A1,A2 for MC14LC5002 Address Inputs The address pins must be tied to VDD. This defines the normal operation mode. CAUTION The configuration A0, A1, A2 = 111 must be used. The config- uration A0, A1, A2 = 000 is reserved for Motorola’s use only. All three address pins should never be tied to 0 V simultaneous- ly. ENB Enable Input If the ENB pin is tied to VDD, the MC14LC5002/5003/5004 will always latch the data after 128 bits have been received. The latched data is multiplexed and fed to the frontplane driv- ers for display. If external control of this latching function is required, then the ENB pin should be held low, followed by one high pulse on ENB when data display is required. (This may be useful in a system where MC14LC5002/5003/5004 is permanently addressed and only the last 128 bits of data sent are required to be latched for display). The pulse on the ENB pin must occur while DCLK is high. DCLK, Din Data Clock and Data Input Address input and data input controls. See Data Input Pro- tocol sections for relevant option. OSC1, OSC2 Oscillator Pins To use the on-board oscillator, an external resistor should be connected between OSC1 and OSC2. Optionally, the OSC1 pin may be driven by an externally generated clock signal. A resistor of 680 k Ω connected between OSC1 and OSC2 pins gives an oscillator frequency of about 30 kHz, giving ap- proximately 30 Hz as seen at the LCD driver outputs. A resistor of 200 k Ω gives about 100 kHz, which results in 100Hz at the driver outputs. LCD manufacturers recommend an LCD drive frequency of between 30 Hz and 100 Hz. See Figure 6. Figure 6. Oscillator Frequency vs. Load Resistance (Approximate) FP1-FP32 Frontplane Drivers Frontplane driver outputs. BP1-BP4 Backplane Drivers Backplane driver outputs. VLCD LCD Driver Supply Power supply input for LCD drive outputs. May be used to supply a temperature-compensated voltage to the LCD drive section, which can be separate from the logic voltage supply, VDD. VDD Positive Power Supply This pin supplies power to the main processor interface and logic portions of the device. The voltage range is 2.7 to 5.5 V with respect to the VSS pin. For optimum performance, VDD should be bypassed to VSS using a low inductance capacitor mounted very closely to these pins. Lead length on this capacitor should be mini- mized. VSS Ground Common ground. 1 k 10 k 100 k 1 M 10 M 10 M 1 M 100 k 10 k OSCILLATOR FREQUENCY |
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