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DAC3282_101 Datasheet(PDF) 7 Page - Texas Instruments

No. de pieza DAC3282_101
Descripción Electrónicos  16-Bit, 625 MSPS, 2x Interpolating, Dual-Channel Digital-to-Analog Converter (DAC)
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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DAC3282_101 Datasheet(HTML) 7 Page - Texas Instruments

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DAC3282
www.ti.com
SLAS646A – DECEMBER 2009 – REVISED FEBRUARY 2010
ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS
(1)
(continued)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD33
3.0
3.3
3.6
V
DACVDD18, DIGVDD18, CLKVDD18
1.7
1.8
1.9
V
I(AVDD33)
Analog supply current
96
mA
I(DIGVDD18)
Digital supply current
268
mA
Mode 1(below)
I(DACVDD18)
DAC supply current
74
mA
I(CLKVDD18)
Clock supply current
10
mA
Power down mode analog supply
I(AVDD33)
2
mA
current
Power down mode digital supply
I(DIGVDD18)
3
mA
current
Mode 4 (below)
Power down mode DAC supply
I(DACVDD18)
0.5
mA
current
Power down mode clock supply
I(CLKVDD18)
1
mA
current
Mode 1: fDAC = 625MSPS, 2x interpolation, mixer on,
950
1100
mW
Digital Offset Control on
Mode 2: fDAC = 491.52MSPS, 2x interpolation, Zero-IF
845
mW
Correction Filter on, mixer off, Digital Offset Control on
Mode 3: Sleep Mode, fDAC = 625MSPS, 2X interpolation,
mixer on,
P
Power Dissipation
575
mW
DAC in sleep mode:
CONFIG24 sleepa, sleepb set to 1
Mode 4: Power-Down mode, No clock, static data pattern,
DAC in power-down mode:
15
mW
CONFIG23 clkpath_sleep_a, clkpath_sleepb set to 1
CONFIG24 clkrecv_sleep, sleepa, sleepb set to 1
PSRR
Power Supply Rejection Ratio
DC tested
–0.4
0.4
%/FSR/V
T
Operating Range
–40
25
85
°C
Copyright © 2009–2010, Texas Instruments Incorporated
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