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LM3S9B95-EQR20-C1T Datasheet(PDF) 10 Page - Texas Instruments

No. de pieza LM3S9B95-EQR20-C1T
Descripción Electrónicos  Stellaris짰 LM3S9B95 Microcontroller
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Fabricante Electrónico  TI [Texas Instruments]
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LM3S9B95-EQR20-C1T Datasheet(HTML) 10 Page - Texas Instruments

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List of Figures
Figure 1-1.
Stellaris
® LM3S9B95 Microcontroller High-Level Block Diagram ............................ 68
Figure 2-1.
CPU Block Diagram ............................................................................................. 71
Figure 2-2.
TPIU Block Diagram ............................................................................................ 79
Figure 5-1.
JTAG Module Block Diagram ................................................................................ 90
Figure 5-2.
Test Access Port State Machine ........................................................................... 93
Figure 5-3.
IDCODE Register Format ..................................................................................... 99
Figure 5-4.
BYPASS Register Format .................................................................................... 99
Figure 5-5.
Boundary Scan Register Format ......................................................................... 100
Figure 6-1.
Basic RST Configuration .................................................................................... 103
Figure 6-2.
External Circuitry to Extend Power-On Reset ....................................................... 104
Figure 6-3.
Reset Circuit Controlled by Switch ...................................................................... 104
Figure 6-4.
Power Architecture ............................................................................................ 107
Figure 6-5.
Main Clock Tree ................................................................................................ 110
Figure 7-1.
Internal Memory Block Diagram .......................................................................... 209
Figure 8-1.
μDMA Block Diagram ......................................................................................... 247
Figure 8-2.
Example of Ping-Pong μDMA Transaction ........................................................... 253
Figure 8-3.
Memory Scatter-Gather, Setup and Configuration ................................................ 255
Figure 8-4.
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 256
Figure 8-5.
Peripheral Scatter-Gather, Setup and Configuration ............................................. 258
Figure 8-6.
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 259
Figure 9-1.
Digital I/O Pads ................................................................................................. 309
Figure 9-2.
Analog/Digital I/O Pads ...................................................................................... 310
Figure 9-3.
GPIODATA Write Example ................................................................................. 311
Figure 9-4.
GPIODATA Read Example ................................................................................. 311
Figure 10-1.
EPI Block Diagram ............................................................................................. 362
Figure 10-2.
SDRAM Non-Blocking Read Cycle ...................................................................... 369
Figure 10-3.
SDRAM Normal Read Cycle ............................................................................... 370
Figure 10-4.
SDRAM Write Cycle ........................................................................................... 371
Figure 10-5.
Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 378
Figure 10-6.
Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 378
Figure 10-7.
Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 1, RDHIGH = 1 ............................................................................................... 379
Figure 10-8.
Continuous Read Mode Accesses ...................................................................... 379
Figure 10-9.
Write Followed by Read to External FIFO ............................................................ 380
Figure 10-10. Two-Entry FIFO ................................................................................................. 380
Figure 10-11. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 384
Figure 10-12. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 384
Figure 10-13. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 385
Figure 10-14. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 385
Figure 10-15. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 385
Figure 10-16. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 386
Figure 10-17. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 386
Figure 10-18. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 386
Figure 10-19. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 386
Figure 10-20. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 387
June 14, 2010
10
Texas Instruments-Advance Information
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