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LM3S8962-IBZ25-A2 Datasheet(PDF) 10 Page - Texas Instruments |
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LM3S8962-IBZ25-A2 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 684 page Figure 15-1. I2C Block Diagram ............................................................................................. 404 Figure 15-2. I2C Bus Configuration ........................................................................................ 404 Figure 15-3. START and STOP Conditions ............................................................................. 405 Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 405 Figure 15-5. R/S Bit in First Byte ............................................................................................ 405 Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 406 Figure 15-7. Master Single SEND .......................................................................................... 409 Figure 15-8. Master Single RECEIVE ..................................................................................... 410 Figure 15-9. Master Burst SEND ........................................................................................... 411 Figure 15-10. Master Burst RECEIVE ...................................................................................... 412 Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 413 Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 414 Figure 15-13. Slave Command Sequence ................................................................................ 415 Figure 16-1. CAN Controller Block Diagram ............................................................................ 440 Figure 16-2. CAN Data/Remote Frame .................................................................................. 441 Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 449 Figure 16-4. CAN Bit Time .................................................................................................... 453 Figure 17-1. Ethernet Controller ............................................................................................. 488 Figure 17-2. Ethernet Controller Block Diagram ...................................................................... 488 Figure 17-3. Ethernet Frame ................................................................................................. 489 Figure 17-4. Interface to an Ethernet Jack .............................................................................. 495 Figure 18-1. Analog Comparator Module Block Diagram ......................................................... 535 Figure 18-2. Structure of Comparator Unit .............................................................................. 536 Figure 18-3. Comparator Internal Reference Structure ............................................................ 536 Figure 19-1. PWM Unit Diagram ............................................................................................ 547 Figure 19-2. PWM Module Block Diagram .............................................................................. 548 Figure 19-3. PWM Count-Down Mode .................................................................................... 549 Figure 19-4. PWM Count-Up/Down Mode .............................................................................. 549 Figure 19-5. PWM Generation Example In Count-Up/Down Mode ........................................... 550 Figure 19-6. PWM Dead-Band Generator ............................................................................... 550 Figure 20-1. QEI Block Diagram ............................................................................................ 585 Figure 20-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 586 Figure 21-1. 100-Pin LQFP Package Pin Diagram .................................................................. 601 Figure 21-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 602 Figure 24-1. Load Conditions ................................................................................................ 637 Figure 24-2. JTAG Test Clock Input Timing ............................................................................. 639 Figure 24-3. JTAG Test Access Port (TAP) Timing .................................................................. 640 Figure 24-4. JTAG TRST Timing ............................................................................................ 640 Figure 24-5. External Reset Timing (RST) .............................................................................. 641 Figure 24-6. Power-On Reset Timing ..................................................................................... 641 Figure 24-7. Brown-Out Reset Timing .................................................................................... 641 Figure 24-8. Software Reset Timing ....................................................................................... 641 Figure 24-9. Watchdog Reset Timing ..................................................................................... 642 Figure 24-10. Hibernation Module Timing ................................................................................. 643 Figure 24-11. ADC Input Equivalency Diagram ......................................................................... 644 Figure 24-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 645 Figure 24-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 645 June 22, 2010 10 Texas Instruments-Production Data Table of Contents |
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