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LM3S8738-IQN50-A2 Datasheet(PDF) 11 Page - Texas Instruments |
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LM3S8738-IQN50-A2 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 616 page List of Tables Table 1. Revision History .................................................................................................. 20 Table 2. Documentation Conventions ................................................................................ 26 Table 3-1. Memory Map ....................................................................................................... 51 Table 4-1. Exception Types .................................................................................................. 53 Table 4-2. Interrupts ............................................................................................................ 54 Table 5-1. JTAG Port Pins Reset State ................................................................................. 58 Table 5-2. JTAG Instruction Register Commands ................................................................... 63 Table 6-1. Clock Source Options .......................................................................................... 73 Table 6-2. Possible System Clock Frequencies Using the SYSDIV Field ................................. 76 Table 6-3. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ............ 76 Table 6-4. System Control Register Map ............................................................................... 80 Table 6-5. RCC2 Fields that Override RCC fields .................................................................. 95 Table 7-1. Hibernation Module Register Map ....................................................................... 141 Table 8-1. Flash Protection Policy Combinations ................................................................. 156 Table 8-2. User-Programmable Flash Memory Resident Registers ....................................... 158 Table 8-3. Flash Register Map ............................................................................................ 159 Table 9-1. GPIO Pad Configuration Examples ..................................................................... 184 Table 9-2. GPIO Interrupt Configuration Example ................................................................ 184 Table 9-3. GPIO Register Map ........................................................................................... 186 Table 10-1. Available CCP Pins ............................................................................................ 223 Table 10-2. 16-Bit Timer With Prescaler Configurations ......................................................... 226 Table 10-3. Timers Register Map .......................................................................................... 232 Table 11-1. Watchdog Timer Register Map ............................................................................ 260 Table 12-1. Samples and FIFO Depth of Sequencers ............................................................ 283 Table 12-2. Differential Sampling Pairs ................................................................................. 285 Table 12-3. ADC Register Map ............................................................................................. 289 Table 13-1. UART Register Map ........................................................................................... 324 Table 14-1. SSI Register Map .............................................................................................. 369 Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ................................... 400 Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 409 Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 414 Table 16-1. CAN Protocol Ranges ........................................................................................ 446 Table 16-2. CANBIT Register Values .................................................................................... 446 Table 16-3. CAN Register Map ............................................................................................. 450 Table 17-1. TX & RX FIFO Organization ............................................................................... 483 Table 17-2. Ethernet Register Map ....................................................................................... 489 Table 18-1. Internal Reference Voltage and ACREFCTL Field Values ..................................... 529 Table 18-2. Analog Comparators Register Map ..................................................................... 530 Table 20-1. Signals by Pin Number ....................................................................................... 540 Table 20-2. Signals by Signal Name ..................................................................................... 544 Table 20-3. Signals by Function, Except for GPIO ................................................................. 548 Table 20-4. GPIO Pins and Alternate Functions ..................................................................... 551 Table 20-5. Signals by Pin Number ....................................................................................... 552 Table 20-6. Signals by Signal Name ..................................................................................... 556 Table 20-7. Signals by Function, Except for GPIO ................................................................. 561 Table 20-8. GPIO Pins and Alternate Functions ..................................................................... 564 11 June 22, 2010 Texas Instruments-Production Data Stellaris® LM3S8738 Microcontroller |
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