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LM3S9781-IQC20-C1 Datasheet(PDF) 4 Page - Texas Instruments

No. de pieza LM3S9781-IQC20-C1
Descripción Electrónicos  Stellaris짰 LM3S9781 Microcontroller
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Fabricante Electrónico  TI [Texas Instruments]
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LM3S9781-IQC20-C1 Datasheet(HTML) 4 Page - Texas Instruments

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5.5.1
Instruction Register (IR) ................................................................................................. 93
5.5.2
Data Registers .............................................................................................................. 95
6
System Control ....................................................................................................... 97
6.1
Signal Description ......................................................................................................... 97
6.2
Functional Description ................................................................................................... 97
6.2.1
Device Identification ...................................................................................................... 98
6.2.2
Reset Control ................................................................................................................ 98
6.2.3
Non-Maskable Interrupt ............................................................................................... 102
6.2.4
Power Control ............................................................................................................. 103
6.2.5
Clock Control .............................................................................................................. 103
6.2.6
System Control ........................................................................................................... 110
6.3
Initialization and Configuration ..................................................................................... 111
6.4
Register Map .............................................................................................................. 112
6.5
Register Descriptions .................................................................................................. 113
7
Internal Memory ................................................................................................... 199
7.1
Block Diagram ............................................................................................................ 199
7.2
Functional Description ................................................................................................. 199
7.2.1
SRAM ........................................................................................................................ 200
7.2.2
ROM .......................................................................................................................... 200
7.2.3
Flash Memory ............................................................................................................. 202
7.3
Flash Memory Initialization and Configuration ............................................................... 203
7.3.1
Flash Memory Programming ........................................................................................ 203
7.3.2
32-Word Flash Memory Write Buffer ............................................................................. 205
7.3.3
Nonvolatile Register Programming ............................................................................... 205
7.4
Register Map .............................................................................................................. 206
7.5
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 207
7.6
Memory Register Descriptions (System Control Offset) .................................................. 218
8
Micro Direct Memory Access (μDMA) ................................................................ 236
8.1
Block Diagram ............................................................................................................ 237
8.2
Functional Description ................................................................................................. 237
8.2.1
Channel Assignments .................................................................................................. 238
8.2.2
Priority ........................................................................................................................ 239
8.2.3
Arbitration Size ............................................................................................................ 239
8.2.4
Request Types ............................................................................................................ 239
8.2.5
Channel Configuration ................................................................................................. 240
8.2.6
Transfer Modes ........................................................................................................... 242
8.2.7
Transfer Size and Increment ........................................................................................ 250
8.2.8
Peripheral Interface ..................................................................................................... 250
8.2.9
Software Request ........................................................................................................ 250
8.2.10 Interrupts and Errors .................................................................................................... 251
8.3
Initialization and Configuration ..................................................................................... 251
8.3.1
Module Initialization ..................................................................................................... 251
8.3.2
Configuring a Memory-to-Memory Transfer ................................................................... 251
8.3.3
Configuring a Peripheral for Simple Transmit ................................................................ 253
8.3.4
Configuring a Peripheral for Ping-Pong Receive ............................................................ 254
8.3.5
Configuring Channel Assignments ................................................................................ 257
8.4
Register Map .............................................................................................................. 257
8.5
μDMA Channel Control Structure ................................................................................. 258
June 29, 2010
4
Texas Instruments-Advance Information
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