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TPS54292PWP Datasheet(PDF) 8 Page - Texas Instruments

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No. de pieza TPS54292PWP
Descripción Electrónicos  1.5-A/2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

TPS54292PWP Datasheet(HTML) 8 Page - Texas Instruments

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16
15
PVDD2
BOOT2
14
13
12
11
SW2
PGND2
BP
GND
10
9
FB2
COMP2
Thermal Pad
(bottom side)
HTSSOP (PWP)
(Top View)
1
2
3
4
PVDD1
BOOT1
SW1
PGND1
5
6
7
EN1
EN2
FB1
8
COMP1
TPS54290, TPS54291, TPS54292
SLUS973 – OCTOBER 2009
www.ti.com
DEVICE INFORMATION
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
Input supply to the high-side gate driver for Output1. Connect a 22 nF to 68 nF capacitor from this pin to
SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON
BOOT1
2
I
during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2
Ω to 5
Ω) may be placed in series with the bootstrap capacitor.
Input supply to the high-side gate driver for Output2. Connect a 22 nF to 68 nF capacitor from this pin to
SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON
BOOT2
15
I
during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2
Ω to 5
Ω) may be placed in series with the bootstrap capacitor.
Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR 4.7-µF (10-µF
BP
12
preferred) ceramic capacitor.
Active-low enable input for Output1. If the voltage on this pin is greater than 1.5 V, Output1 is disabled
(high-side switch is OFF). A voltage of less than 0.9 V enables Output1 and allow soft start of Output1 to
EN1
5
I
begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass
the enable function.
Active-low enable input for Output2. If the voltage on this pin is greater than 1.5 V, Output2 is disabled
(high-side switch is OFF). A voltage of less than 0.9 V enables Output2 and allow soft-start of Output2 to
EN2
6
I
begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass
the enable function.
FB1
7
I
Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx
to regulate the voltage at this pin to the internal 0.8 V reference. A series resistor divider from Outputx to
FB2
10
I
ground, with the center connection tied to this pin, determines the value of the regulated output voltage.
COMP1
8
O
Output of the transconductance (gM) amplifier. A R-C compensation network is connected from COMPx to
GND.
COMP2
9
O
PGND1
4
Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal
logic circuits.
PGND2
13
GND
11
Analog ground pin for the device.
Power input to the Output1 high-side MOSFET only. This pin should be locally bypassed to PGND1 with a
PVDD1
1
I
low ESR ceramic capacitor of 10 µF or greater. PVDD1 and PVDD2 could be tied externally together.
The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins
and provides power to the Output2 high-side MOSFET. This pin should be locally bypassed to PGND2 with
PVDD2
16
I
a low ESR ceramic capacitor of 10 µF or greater. The UVLO function monitors PVDD2 and enables the
device when PVDD2 is greater than 4.2 V.
SW1
3
O
Source (switching) output for Output1 PWM.
SW2
14
O
Source (switching) output for Output2 PWM.
Thermal Pad
This pad must be tied externally to a ground plane.
8
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Product Folder Link(s) :TPS54290 TPS54291 TPS54292


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