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TPS54290, TPS54291, TPS54292

SLUS973 – OCTOBER 2009

www.ti.com

APPLICATION INFORMATION

FUNCTIONAL DESCRIPTION

The TPS54290/1/2 is a dual output fully synchronous buck converter. Each PWM channel contains an error

amplifier, current mode pulse width modulator (PWM), switching and rectifying MOSFETs, enable, and fault

protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, and clock

oscillator.

VOLTAGE REFERENCE

The band gap cell common to both outputs, trimmed to 800 mV. The reference voltage is 1% accurate in the

temperature range from 0°C to 85°C.

OSCILLATOR

The oscillator frequency is internally fixed at 2.4 MHz which is divided by 8/4/2 to generate the ramps for

TPS54290/1/2 respectively. The two outputs are internally configured to operate on alternating switch cycles (i.e.,

180° out-of-phase).

INPUT UVLO AND STARTUP

When the voltage at the PVDD2 pin is less than 4.4 V, a portion of the internal bias circuitry is operational, and

all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises

above the UVLO turn on threshold, the state of the enable pins determines the remainder of the internal startup

sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with

a 20 mA current. When the BP pin is greater than 4 V, PWM is enabled and soft-start commences.

Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be

higher or lower than PVDD2.

ENABLE AND TIMED TURN ON OF THE OUTPUTS

Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to

PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.25 V with an external circuit, the

associated output is enabled and soft-start is initiated.

If both enable pins are left in the “high” state, the device operates in a shutdown mode, where the BP regulator is

shut down and minimal house keeping functions are active. The total standby current from both PVDD pins is

80 µA at 12 V input supply.

An R-C connect to an ENx pin may be used to delay the turn on of the associated output after power is applied

to PVDDx (see Figure 12). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards

ground. Once the voltage decays to approximately 1.25 V, then the output is enabled and the startup sequence

begins. If it is desired to enable the outputs of the device immediately upon the application of power to the

PVDD2 pin, then omit these two components and tie the ENx pin to GND directly.

If an R-C circuit is used to delay the turn on of the output, the resistor value must be an order of magnitude less

than 1.25 V/10 µA or 120 k

Ω. A suggested value is 51 kΩ. This allows the ENx voltage to decay below the 1.25

V threshold while the 10-µA bias current flows.

The time to start (after the application of PVDD2) is

(1)

where

•

R and C are the timing components

•

•

Figure 12 and Figure 13 illustrate startup delay with an R-C filter on the enable pin(s).

10

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Product Folder Link(s) :TPS54290 TPS54291 TPS54292