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BU9252S Datasheet(PDF) 5 Page - Rohm |
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BU9252S Datasheet(HTML) 5 Page - Rohm |
5 / 6 page 5 Multimedia ICs BU9252S / BU9252F •Circuit operation (1) External capacitor for signal input pin Audio signals compressed by the BA7725S or BA7725FS have their DC component removed by an AC coupling capacitor and are then input to pin 2 of BU9252S or BU9252F. At this stage, level deviations occur because the input signal is capacitor-divided by this AC coupling capacitor C28 and by sampling hold capacitor C27 connected to pin 1. To prevent this, make sure that C27 is much lower than C28. (Note: The numbers of external components are the numbers used in the sys- tem application example.) (3) Delay timer settings The delay time (i.e., the length of time the signal is stored in the SRAM) can be set to any of eight settings between the maximum and minimum delay times by setting pins 6, 7 and 8 to the combination of logic sig- nal inputs that results in the corresponding number of counts. The maximum and minimum delay times are determined by the oscillation frequency of the attached ceramic resonator. 1 2 S / H C27 C28 The sample-held analog signal is converted to digital by the serial 8-bit A / D converter and then temporarily stored in the internal SRAM (2k bytes). (2) Relationship between oscillation frequency (CLK) and delay time Sample rate F = fOSC / 32 (fosc: oscillation frequency) F = 14.22kHz at fosc = 455kHz Sample period T = 1 / F Delay time Dtime = T × number of counts The delay time can be set to any of the eight settings shown below by setting the logic inputs of terminals DCNT0 through DCNT2. Logic input Count DCNT1 DCNT2 DCNT0 BU9252S / F 0 0 0 256 18.00 0 0 1 512 36.01 0 1 0 768 54.01 0 1 1 1024 72.02 1 0 0 1280 90.02 1 0 1 1536 108.03 1 1 0 1792 126.03 1 1 1 2048 144.04 BU9252S / F Delay time (ms) (when fOSC = 455kHz) CC C (t) (dB) C : Delay time (ms) |
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