KM48V8004C,KM48V8104C

CMOS DRAM

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before

proper device operation is achieved.

Measured with a load equivalent to 1 TTL load and 100pF.

Operation within the

If

Assumes that

teristics only. If

duration of the cycle. If

and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the

condition of the data out is indeterminate.

Either

This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in OE controlled write

cycle and read-modify-write cycles.

Operation within the

These specifications are applied in the test mode.

In test mode read cycle, the value of

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.

If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.

If

For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed

within 64ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before

and after self refresh in order to meet refresh specification.

5.

6.

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8.

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1.

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14.

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17.