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KM681002CJ-15 Datasheet(PDF) 5 Page - Samsung semiconductor |
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KM681002CJ-15 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page KM681002C/CL, KM681002CI/CLI CMOS SRAM PRELIMINARY Revision 2.0 - 5 - March 2000 PRELIMINARY WRITE CYCLE* * The above parameters are also guaranteed at industrial temperature range. Parameter Symbol KM681002C-10 KM681002C-12 KM681002C-15 KM681002C-20 Unit Min Max Min Max Min Max Min Max Write Cycle Time tWC 10 - 12 - 15 - 20 - ns Chip Select to End of Write tCW 7 - 8 - 9 - 10 - ns Address Set-up Time tAS 0 - 0 - 0 - 0 - ns Address Valid to End of Write tAW 7 - 8 - 9 - 10 - ns Write Pulse Width(OE High) tWP 7 - 8 - 9 - 10 - ns Write Pulse Width(OE Low) tWP1 10 - 12 - 15 - 20 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 5 0 6 0 7 0 9 ns Data to Write Time Overlap tDW 5 - 6 - 7 - 8 - ns Data Hold from Write Time tDH 0 - 0 - 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - 3 - 3 - ns Address Data Out Previous Valid Data Valid Data TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tAA tRC tOH TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) CS Address OE Data out tAA tOLZ tLZ(4,5) tOH tOHZ tRC tOE tCO tPU tPD Valid Data tHZ(3,4,5) 50% 50% VCC Current ICC ISB |
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Descripción similar - KM681002CJ-15 |
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