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SN74AUP1G02DBVTE4 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74AUP1G02DBVTE4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 21 page −0.5 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 Time − ns Output Input Switching Characteristics at 25 MHz† † AUP1G08 data at CL = 15 pF AUP LVC AUP AUP LVC Static-Power Consumption ( µA) Dynamic-Power Consumption (pF) † Single, dual, and triple gates 3.3-V Logic† 3.3-V Logic† 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% Y = + or Y = • A B A B SN74AUP1G02 SCES568G – JUNE 2004 – REVISED MARCH 2010 www.ti.com Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity This single 2-input positive-NOR gate performs the Boolean function in positive logic. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP1G02YFPR _ _ _ H B _ 0.23-mm Large Bump – YFP (Pb-free) QFN – DRY Reel of 5000 SN74AUP1G02DRYR HB uQFN – DSF Reel of 5000 SN74AUP1G02DSFR HB –40°C to 85°C SOT (SOT-23) – DBV Reel of 3000 SN74AUP1G02DBVR H02_ SOT (SC-70) – DCK Reel of 3000 SN74AUP1G02DCKR HB_ SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G02DRLR HB_ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS OUTPUT Y A B L L H L H L H L L H H L LOGIC DIAGRAM (POSITIVE LOGIC) 2 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G02 |
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