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ADSP-BF592KCPZ-X Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-BF592KCPZ-X Datasheet(HTML) 1 Page - Analog Devices |
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1 / 46 page  Preliminary Technical Data Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin Embedded Processor ADSP-BF592 Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved. FEATURES Up to 400 MHz high-performance Blackfin processor 2 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Accepts a wide range of supply voltages for internal and I/O operations. See Operating Conditions on Page 18 Off-chip voltage regulator interface 64-lead (9 mm × 9 mm) LFCSP package MEMORY 68K bytes of core-accessible memory: (See Table 1 on Page 3 for L1 and L3 memory size details) 64K byte L1 instruction ROM Flexible booting options from internal L1 ROM and SPI mem- ory or from host devices including SPI, PPI, and UART Memory management unit providing memory protection PERIPHERALS 4 32-bit timers/counters, three with PWM support 2 dual-channel, full-duplex synchronous serial ports (SPORT), supporting eight stereo I 2S channels 2 Serial Peripheral Interface (SPI) compatible ports 1 UART with IrDA support Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats Two-wire interface (TWI) controller 9 peripheral DMAs 2 memory-to-memory DMA channels Event handler with 28 interrupt inputs 32 general-purpose I/Os (GPIOs), with programmable hysteresis Debug/JTAG interface On-chip PLL capable of frequency multiplication Figure 1. Processor Block Diagram SPORT0 VOLTAGE REGULATOR INTERFACE PORT F JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS WATCHDOG TIMER PPI SPI0 SPI1 BOOT ROM DMA ACCESS BUS INTERRUPT CONTROLLER DMA CONTROLLER L1 DATA SRAM L1 INSTRUCTION SRAM DCB B UART DEB TIMER2–0 L1 INSTRUCTION ROM GPIO SPORT1 TWI PORT G |
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