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SST25VF032B-66-4I-S2F Datasheet(PDF) 17 Page - Silicon Storage Technology, Inc |
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SST25VF032B-66-4I-S2F Datasheet(HTML) 17 Page - Silicon Storage Technology, Inc |
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17 / 28 page  Data Sheet 32 Mbit SPI Serial Flash SST25VF032B 17 ©2009 Silicon Storage Technology, Inc. S71327-03-000 05/09 Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of the status regis- ter. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to ‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status register, but cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 and BP2 bits in the status register can all be changed. As long as BPL bit is set to ‘0’ or WP# pin is driven high (VIH) prior to the low-to- high transition of the CE# pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as altering the BP0, BP1, and BP2 bits at the same time. See Table 2 for a summary description of WP# and BPL functions. FIGURE 19: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence 1327 F20.0 MODE 3 HIGH IMPEDANCE MODE 0 STATUS REGISTER IN 7 6 5 4321 0 MSB MSB MSB 01 MODE 3 SCK SI SO CE# MODE 0 50 or 06 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
Número de pieza similar - SST25VF032B-66-4I-S2F |
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