11

FN6716.0

June 4, 2008

drawing current from the external TMDS receiver it is

attached to.

This is non-ideal and can cause the ISL54105A to fail HDMI

each 50

Ω Rx

device containing the ISL54105A.

To prevent this leakage current, insert a Schottky diode

in Figure 9. With the addition of this diode the system will

pass compliance test 7-3.

Inter-Pair (Channel-to-Channel) Skew

The read pointers for Channel 0, 1, and 2 of the FIFO that

follows the CDR all have the same clock, so all 3 channels

transition within a few picoseconds of each other - there is

essentially no skew between the transitions of the three

channels.

However the FIFO read pointers may be positioned up to 2

bits apart relative to each other, introducing a random, fixed

channel-to-channel skew of skew of 1 or (much less

frequently) 2 bits. The random skew is introduced whenever

there is a discontinuity in the input signal (typically a video

mode change or a new mux channel selection). After the

CDRs and PLL lock, the skew is fixed until the next

discontinuity. This adds up to 2 bits of skew in addition to any

incoming skew, as shown in the following examples.

Figure 10 shows an input (the top three signals) with

essentially no skew. After the ISL54105A locks on to the

signal, there may be 1 bit of skew on the output, as shown in

Figure 10.

When there is pre-existing skew on the input, the ISL54105A

can add up to 2 bits to the channel-to-channel skew. In the

example in Figure 11, the incoming red channel has 2.3 bits

of skew relative to the incoming green and blue. The FIFO’s

quantization (worst case) increases the total skew to 4.0 bits.

While increasing skew is not desirable, DVI and HDMI

receivers are required to have a minimum of 6 bits of inter-

pair skew tolerance, so the addition of 2 bits of skew is only a

problem with the most pathological cables and transmitters.

It does, however, limit the number of ISL54105As that can

be put in series (although statistically it is unlikely that all the

skews would line up in a worst-case configuration).

FIGURE 8. ISL54105A ESD PROTECTION DIODES

ISL54105A

(41, 53)

Tx

50

FIGURE 9. SCHOTTKY DIODE MODIFICATION

ISL54105A

(41, 53)

Tx

50

0.1

μF

FIGURE 10. MAXIMUM ADDITIONAL INTERCHANNEL SKEW

FOR INPUTS WITH NO OR LITTLE SKEW

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

B

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

B

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

B

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 0

Bit 1

Bit 2

Bit 3

B

Bit 7

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

B

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

B

Bit 8

Bit 9

INPUT SKEW

(none, in this

example)

OUTPUT SKEW

(1 bit – 615ps at

162.5Mpixels/s)

FIGURE 11. MAXIMUM ADDITIONAL INTERCHANNEL SKEW

FOR INPUTS WITH MODERATE TO LARGE

SKEW

Bit 4

Bit 5

Bit 0

Bit 1

Bit 2

Bit 3

Bit 7

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 7

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 7

Bit 8

Bit 9

Bit 4

Bit 0

Bit 1

Bit 2

Bit 3

Bit 6

Bit 7

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 7

Bit 8

Bit 9

Bit 4

Bit 5

Bit 6

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 8

Bit 9

INPUT SKEW

(2.3 bits/1.4ns

in this example)

OUTPUT SKEW

(4 bits/2.5ns at

162.5Mpixels/s)

Bit 5

Bit 6

Bit 4

Bit 5

Bit 8

ISL54105A