ISL12023IVZ datasheet(10/28 Pages) INTERSIL

No. de pieza	ISL12023IVZ

Descripción Electrónicos	Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation 짹5ppm with Auto Daylight Saving

Download	28 Pages

Scroll/Zoom	100%

Fabricante Electrónico	INTERSIL [Intersil Corporation]

Página de inicio	http://www.intersil.com/cda/home

Logo

10 / 28 page

10

FN6682.2

June 24, 2009

The device Time Stamps the switchover from VDD to VBAT

and VBAT to VDD, and the time is stored in tSV2B and tSB2V

registers respectively. If multiple VDD power-down

sequences occur before status is read, the earliest VDD to

VBAT power-down time is stored and the most recent VBAT

to VDD time is stored.

Temperature conversion and compensation can be enabled

in battery-backup mode. Bit BTSE in the BETA register

controls this operation, as described in “BETA Register

(BETA)” on page 17.

Power Failure Detection

The ISL12023 provides a Real Time Clock Failure Bit

(RTCF) to detect total power failure. It allows users to

determine if the device has powered up after having lost all

power to the device (both VDD and VBAT).

Brownout Detection

The ISL12023 monitors the VDD level continuously and

provides warning if the VDD level drops below prescribed

levels. There are six (6) levels that can be selected for the

trip level. These values are 85% below popular VDD levels.

The LVDD bit in the Status Register will be set to “1” when

brownout is detected. Note that the I2C serial bus remains

active unless the Battery VTRIP levels are reached. The

LVRST output becomes active (LOW) when the Power

Brownout Bit (LVDD) is set.

When the VDD power is re-established and is above the 85%

VDD + 50mV trip point, the LVRST output is set HIGH. The

LVDD bit is reset once it is read by the Micro. Note that the

I2C serial bus remains active unless the Battery VTRIP levels

are reached.

Battery Level Monitor

The ISL12023 has a built in warning feature once the backup

battery level drops first to 85% and then to 75% of the

battery’s nominal VBAT level. When the battery voltage

drops to between 85% and 75%, the LBAT85 bit is set in the

status register. When the level drops below 75%, both

LBAT85 and LBAT75 bits are set in the status register.

The battery level monitor is not functional in battery backup

mode. In order to read the monitor bits after powering up

VDD, instigate a battery level measurement by setting the

TSE bit to "1" (BETA register), and then read the bits.

There is a Battery Time Stamp Function available. Once the

VDD is low enough to enable switchover to the battery, the

RTC time/date are written into the TSV2B register. This

information can be read from the TSV2B registers to

discover the point in time of the VDD power-down. If there

are multiple power-down cycles before reading these

registers, the first values stored in these registers will be

retained. These registers will hold the original power-down

value until they are cleared by setting CLRTS = 1 to clear the

registers.

The normal power switching of the ISL12023 is designed to

switch into battery-backup mode only if the VDD power is

lost. This will ensure that the device can accept a wide range

of backup voltages from many types of sources while reliably

switching into backup mode.

Note that the ISL12023 is not guaranteed to operate with

VBAT < 1.8V. If the battery voltage is expected to drop lower

than this minimum, correct operation of the device,

especially after a VDD power down cycle, is not guaranteed.

The minimum VBAT to insure SRAM is stable is 1.0V. Below

that, the SRAM may be corrupted when VDD power resumes.

Real Time Clock Operation

The Real Time Clock (RTC) uses an external 32.768kHz

quartz crystal to maintain an accurate internal representation

of second, minute, hour, day of week, date, month, and year.

The RTC also has leap-year correction. The clock also

corrects for months having fewer than 31 days and has a bit

that controls 24-hour or AM/PM format. When the ISL12023

powers up after the loss of both VDD and VBAT, the clock will

not begin incrementing until at least one byte is written to the

clock register.

Single Event and Interrupt

The alarm mode is enabled via the MSB bit. Choosing single

event or interrupt alarm mode is selected via the IM bit. Note

that when the frequency output function is enabled, the

alarm function is disabled.

The standard alarm allows for alarms of time, date, day of

the week, month, and year. When a time alarm occurs in

single event mode, an IRQ pin will be pulled low and the

alarm status bit (ALM) will be set to “1”.

The pulsed interrupt mode allows for repetitive or recurring

alarm functionality. Hence, once the alarm is set, the device

will continue to alarm for each occurring match of the alarm

and present time. Thus, it will alarm as often as every minute

(if only the nth second is set) or as infrequently as once a

year (if at least the nth month is set). During pulsed interrupt

mode, the IRQ pin will be pulled low for 250ms and the alarm

status bit (ALM) will be set to “1”.

The ALM bit can be reset by the user or cleared

automatically using the auto reset mode (see ARST bit). The

alarm function can be enabled/disabled during

battery-backup mode using the FOBATB bit. For more

information on the alarm, please see “ALARM Registers

(10h to 15h)” on page 19.

Frequency Output Mode

The ISL12023 has the option to provide a clock output signal

using the FOUT open drain output pin. The frequency output

mode is set by using the FO bits to select one of 15 possible

output frequency values from 1/32Hz to 32kHz. The

frequency output can be enabled/disabled during

battery-backup mode using the FOBATB bit.

ISL12023

Número de pieza similar - ISL12023IVZ

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Renesas Technology Corp	ISL12023IVZ	1Mb / 29P	Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation 짹5ppm with Auto Daylight Saving

More results

Descripción similar - ISL12023IVZ

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Renesas Technology Corp	ISL12023	1Mb / 29P	Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation 짹5ppm with Auto Daylight Saving
Renesas Technology Corp	ISL12022	1Mb / 29P	Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation 짹5ppm with Auto Daylight Saving
Intersil Corporation	ISL12020M	476Kb / 32P	Low Power RTC with Battery Backed SRAM, Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving
Intersil Corporation	ISL12022MIBZ-T7A	900Kb / 31P	Low Power RTC with Battery Backed SRAM, Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving
Renesas Technology Corp	ISL12022MA	1Mb / 31P	Low Power RTC with Battery Backed SRAM, Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving
	ISL12022MR5421	1Mb / 31P	Low Power RTC with Battery Backed SRAM, Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving
	ISL12020M	1Mb / 34P	Low Power RTC with Battery Backed SRAM, Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving
Intersil Corporation	ISL12022M	620Kb / 31P	Low Power RTC with Battery Backed SRAM,Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving
	ISL12022MA	866Kb / 29P	Low Power RTC with Battery Backed SRAM, Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving
	ISL12020MIRZ-T7A	633Kb / 34P	Low Power RTC with Battery Backed SRAM, Integrated 짹5ppm Temperature Compensation and Auto Daylight Saving

More results

ISL12023IVZ Datasheet(PDF) 10 Page - Intersil Corporation

ISL12023IVZ Datasheet(HTML) 10 Page - Intersil Corporation

Número de pieza similar - ISL12023IVZ

Descripción similar - ISL12023IVZ

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Descarga

Enlace URL