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LM5041ASD Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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LM5041ASD Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 16 page  Pin Description (Continued) PIN NAME DESCRIPTION APPLICATION INFORMATION 9 PULL Output of the push-pull drivers Output of the push-pull gate driver. Output capability of 1.5A peak. 10 PGND Power ground Connect directly to analog ground. 11 AGND Analog ground Connect directly to power ground. 12 CS Current sense input Current sense input to the PWM comparator (CM control). There is a 50ns leading edge blanking on this pin. Using separate dedicated comparator, if CS exceeds 0.5V the outputs will go into cycle by cycle current limit. 13 SS Soft-start control An external capacitor and an internal 10uA current source, set the soft-start ramp. 14 TIME Push-Pull overlap and dead time control An external resistor (R SET) sets the overlap time or dead time for the push-pull outputs. A resistor connected between TIME and GND produces overlap. A resistor connected between TIME and REF produces dead time. 15 RT / SYNC Oscillator timing resistor pin and sync An external resistor sets the oscillator frequency. This pin will also accept an external oscillator. 16 UVLO Line Under-Voltage Shutdown An external divider from the power converter source sets the shutdown levels. Threshold of operation equals 2.5V. Hysteresis is set by a switched internal current source (20µA). LLP DAP SUB Die substrate The exposed die attach pad on the LLP package should be connected to a PCB thermal pad at ground potential. For additional information on using National Semiconductor’s No Pull Back LLP package, please refer to LLP Application Note AN-1187. www.national.com 3 |
Número de pieza similar - LM5041ASD |
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Descripción similar - LM5041ASD |
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