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TPA2015D1 Datasheet(PDF) 22 Page - Texas Instruments |
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TPA2015D1 Datasheet(HTML) 22 Page - Texas Instruments |
22 / 27 page Copper Trace Width Solder Mask Thickness Solder Pad Width Solder Mask Opening Copper Trace Thickness TPA2015D1 SLOS638 – MAY 2010 www.ti.com BOARD LAYOUT In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 28 and Table 5 show the appropriate diameters for a WCSP layout. Figure 28. Land Pattern Dimensions Table 5. Land Pattern Dimensions(1) (2) (3) (4) SOLDER PAD COPPER SOLDER MASK (5) COPPER STENCIL (6) (7) STENCIL DEFINITIONS PAD OPENING THICKNESS OPENING THICKNESS Nonsolder mask 275 mm 275 mm x 275 mm Sq. 375 mm (+0.0, -25 mm) 1 oz max (32 mm) 125 mm thick defined (NSMD) (+0.0, -25 mm) (rounded corners) (1) Circuit traces from NSMD defined PWB lands should be 75 mm to 100 mm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability. (2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application. (3) Recommend solder paste is Type 3 or Type 4. (4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance. (5) Solder mask thickness should be less than 20 mm on top of the copper circuit pattern (6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. (7) Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces. TRACE WIDTH Recommended trace width at the solder balls is 75 mm to 100 mm to prevent solder wicking onto wider PCB traces. For high current pins (SW, GND, OUT+, OUT–, PVOUT, and PVDD) of the TPA2015D1, use 100 mm trace widths at the solder balls and at least 500 mm PCB traces to ensure proper performance and output power for the device. For low current pins (IN–, IN+, END, ENB, GAIN, AGC, VBAT) of the TPA2015D1, use 75 mm to 100 mm trace widths at the solder balls. Run IN- and IN+ traces side-by-side (and if possible, same length) to maximize common-mode noise cancellation. 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPA2015D1 |
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